diff -urN u-boot-1.0.0/board/soca7210/config.mk u-boot-1.0.0-7210/board/soca7210/config.mk --- u-boot-1.0.0/board/soca7210/config.mk 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/config.mk 2003-11-28 17:43:35.000000000 +0900 @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x41200000 diff -urN u-boot-1.0.0/board/soca7210/flash.c u-boot-1.0.0-7210/board/soca7210/flash.c --- u-boot-1.0.0/board/soca7210/flash.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/flash.c 2004-06-01 16:48:02.000000000 +0900 @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define FLASH_BANK_SIZE 0x1000000 +#define MAIN_SECT_SIZE 0x20000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; + } + + size += flash_info[i].size; + } + + /* + Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf ("28F128J3 (128Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + +// printf("unlocking sector\n"); +// *addr = 0x0060; +// *addr = 0x00d0; +// *addr = 0x00ff; + +// *addr = 0x0050; /* clear status register */ + *addr = 0x0020; /* erase setup */ + *addr = 0x00D0; /* erase confirm */ + + while ((*addr & 0x0080) != 0x0080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + + *addr = 0x00B0; /* suspend erase */ + *addr = 0x00FF; /* reset to read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + + /* clear status register command */ + *addr = 0x0050; + /* reset to read mode */ + *addr = 0x00FF; + } + printf ("ok.\n"); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest, val; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* clear status register command */ + *addr = 0x0050; + + /* program set-up command */ + *addr = 0x0040; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((val = *addr) & 0x0080) != 0x0080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + /* suspend program command */ + *addr = 0x00B0; + goto outahere; + } + } + + if (val & 0x1A) { /* check for error */ + printf ("\nFlash write error %02x at address %08lx\n", + (int) val, (unsigned long) dest); + if (val & (1 << 3)) { + printf ("Voltage range error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if (val & (1 << 1)) { + printf ("Device protect error.\n"); + rc = ERR_PROTECTED; + goto outahere; + } + if (val & (1 << 4)) { + printf ("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + + outahere: + /* read array command */ + *addr = 0x00FF; + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff -urN u-boot-1.0.0/board/soca7210/Makefile u-boot-1.0.0-7210/board/soca7210/Makefile --- u-boot-1.0.0/board/soca7210/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/Makefile 2004-01-26 11:13:46.000000000 +0900 @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := soca7210.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff -urN u-boot-1.0.0/board/soca7210/memsetup.S u-boot-1.0.0-7210/board/soca7210/memsetup.S --- u-boot-1.0.0/board/soca7210/memsetup.S 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/memsetup.S 2004-03-30 14:16:09.000000000 +0900 @@ -0,0 +1,175 @@ +/* + * Memory Setup stuff - taken from ??? + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#define SDRAM_CTRL 0x00e200cc +#define SDRAM_CTRL_CAS2_R 0x00a200cc +#define SDRAM_CTRL_CAS2_NR 0x002200cc + + +/* some parameters for the board */ + +/* setting up the memory */ +.globl memsetup +memsetup: + +/* + static memory config cs0 +*/ + ldr r0,=0x80020000 + ldr r2,=0x00001000 /*; Boot Done bit = 1*/ + ldr r1, [r0, #0x04] + orr r1, r1, r2 + str r1, [r0, #0x04] + + ldr r2,=0x00001003 + and r1, r1, r2 + orr r1, r1, #0x40 /*;NORMAL ACCESS WAIT STATE:[8]*/ + str r1, [r0, #0x04] + + ldr r2,=0x0fff + and r1, r1, r2 + str r1, [r0, #0x04] + + + +/* + static memory config cs1 16bit, 8 waits +*/ + ldr r1, =0x80020000 + ldr r2, =0x1000 + ldr r0, =0x41 + orr r3, r2, r0 + str r2, [r1,#0x08] + str r3, [r1,#0x08] + str r0, [r1,#0x08] + +/* + static memory config cs2 16bit, 8 waits +*/ + str r2, [r1,#0x0c] + str r3, [r1,#0x0c] + str r0, [r1,#0x0c] +/* + static memory config cs3 16bit, 8 waits +*/ + str r2, [r1,#0x10] + str r3, [r1,#0x10] + str r0, [r1,#0x10] + + ldr r2, =SDRAM_CTRL + mov r1, #0x80000000 + ldr r3, [r1, #0] + cmp r3, r2 + beq 50f + +/* + idle status,CAS latency2:2(check SDRAM DataSheet),Write buffer enable + E[1:0] = 00, R = 0 +*/ + ldr r1, =SDRAM_CTRL_CAS2_NR + mov r2, #0x80000000 + str r1, [r2, #0] + + mov r1, #0x10000 +10: + sub r1, r1, #1 + cmp r1, #0 + bne 10b +/* + precharge + E[1:0] = 01, R = 0 +*/ + ldr r1, =SDRAM_CTRL_CAS2_NR + add r1,r1, #0x08 + mov r2, #0x80000000 + str r1, [r2, #0] + + mov r1, #0x10000 +20: + sub r1, r1, #1 + cmp r1, #0 + bne 20b + +/* + IO_SdramRefresh = 0x10; +*/ + mov r2, #0x10 + mov r1, #0x80000000 + str r2, [r1, #4] + +/* + auto refresh + E[1:0] = 00, R = 1 +*/ + ldr r1, =SDRAM_CTRL_CAS2_R + mov r2, #0x80000000 + str r1, [r2, #0] + + mov r1, #0x10000 +30: + sub r1, r1, #1 + cmp r1, #0 + bne 30b + +/* + SDRAM Mode Register Setting + Tmp = IO(SdramModeReg | SdramModeBurstLength8 | SdramModeCAS2 |Device0); +*/ + mov r1, #0x10000 /* SDRAM_CASL */ + add r1, r1, #0x1800 /* SDRAM_MODE_BL8 */ + add r1, r1, #0x44000000 + ldr r1, [r1, #0] + mov r0, r1 + + ldr r2, =SDRAM_CTRL + mov r1, #0x80000000 + str r2, [r1, #0] + + mov r2, #1 + mov r1, #0x80000000 + str r2, [r1, #8] +/* + Refresh Value = 0x320 for 16MB(128Mbit)x2 + Refresh Value = 0x320/2 for 32MB(256Mbit)x2 + For simplicity, Refresh value for 32MBx2 is used, and it would + be no problem for 16MBx2 + 0x320 >> 1 = 0x190 +*/ + mov r2, #0x190 + mov r1, #0x80000000 + str r2, [r1, #4] + + mov r1, #0x10000 +10: + sub r1, r1, #1 + cmp r1, #0 + bne 10b + + +50: + + /* everything is fine now */ + mov pc, lr + diff -urN u-boot-1.0.0/board/soca7210/soca7210.c u-boot-1.0.0-7210/board/soca7210/soca7210.c --- u-boot-1.0.0/board/soca7210/soca7210.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/soca7210.c 2004-05-20 13:51:32.000000000 +0900 @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number MACH_TYPE_H7210 */ + gd->bd->bi_arch_number = 440; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0x40001000; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +int smcebiconf_val; + +void nand_init(void) +{ + int val; + + val = (MEMCFG_MEM_WIDTH_8 | ((1 << 3) & MEMCFG_NORMAL_ACCESS_WAIT_STATE_MASK)); + _outw(BANK3_REG,MEMCFG_BT_DONE); + _outw(BANK3_REG,(val | MEMCFG_BT_DONE)); + _outw(BANK3_REG,(val & ~MEMCFG_BT_DONE)); + + _outw(SMC_SMCCONF,SMC_SMCCONF_POWER_ENABLE|SMC_SMCCONF_SMC_ENABLE); + smcebiconf_val = SMC_SMCEBICONF_EBI_SELECT|SMC_SMCEBICONF_WP|SMC_SMCEBICONF_CE; + _outw(SMC_SMCEBICONF,smcebiconf_val); + + // for rb:GPIO_CEN_PORTC1,CD:GPIO_CEN_PORTC0 + _outw(GPIO_CEN, (_inw(GPIO_CEN) | GPIO_CEN_PORTC1 | GPIO_CEN_PORTC0) ); + _outw(GPIO_CDIR, (_inw(GPIO_CDIR) | GPIO_CEN_PORTC1 | GPIO_CEN_PORTC0) ); + + nand_probe(CFG_NAND_BASE); + + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff -urN u-boot-1.0.0/board/soca7210/u-boot.lds u-boot-1.0.0-7210/board/soca7210/u-boot.lds --- u-boot-1.0.0/board/soca7210/u-boot.lds 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/board/soca7210/u-boot.lds 2004-01-26 11:12:15.000000000 +0900 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/hms30c7210/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + armboot_end_data = .; + + . = ALIGN(4); + .bss : { *(.bss) } + + armboot_end = .; +} diff -urN u-boot-1.0.0/common/cmd_date.c u-boot-1.0.0-7210/common/cmd_date.c --- u-boot-1.0.0/common/cmd_date.c 2003-07-02 06:07:07.000000000 +0900 +++ u-boot-1.0.0-7210/common/cmd_date.c 2004-05-20 10:36:27.000000000 +0900 @@ -30,9 +30,15 @@ #if (CONFIG_COMMANDS & CFG_CMD_DATE) +#ifdef CONFIG_SOCA7210 +const char *weekdays[] = { + "Satur", "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", +}; +#else const char *weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; +#endif #define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) diff -urN u-boot-1.0.0/common/cmd_mem.c u-boot-1.0.0-7210/common/cmd_mem.c --- u-boot-1.0.0/common/cmd_mem.c 2003-09-18 18:21:35.000000000 +0900 +++ u-boot-1.0.0-7210/common/cmd_mem.c 2004-03-29 15:00:49.000000000 +0900 @@ -88,7 +88,7 @@ #define DISP_LINE_LEN 16 int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr, length; + volatile ulong addr, length; ulong i, nbytes, linebytes; u_char *cp; int size; diff -urN u-boot-1.0.0/common/cmd_nand.c u-boot-1.0.0-7210/common/cmd_nand.c --- u-boot-1.0.0/common/cmd_nand.c 2003-09-12 04:50:27.000000000 +0900 +++ u-boot-1.0.0-7210/common/cmd_nand.c 2004-05-25 14:46:13.000000000 +0900 @@ -27,6 +27,10 @@ void archflashwp(void *archdata, int wp); #endif +#ifdef CONFIG_SOCA7210 +extern int smcebiconf_val; +#endif + #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) /* @@ -56,8 +60,10 @@ */ #define ALLOW_ERASE_BAD_DEBUG 0 -#define CONFIG_MTD_NAND_ECC /* enable ECC */ -#define CONFIG_MTD_NAND_ECC_JFFS2 +/* #define CONFIG_MTD_NAND_ECC */ /* enable ECC */ +/* #define CONFIG_MTD_NAND_ECC_JFFS2 */ +#undef CONFIG_MTD_NAND_ECC /* disable ECC */ +#undef CONFIG_MTD_NAND_ECC_JFFS2 /* bits for nand_rw() `cmd'; or together as needed */ #define NANDRW_READ 0x01 @@ -276,8 +282,10 @@ ulong cnt; ulong addr; ulong offset = 0; + ulong offset1 = 0; image_header_t *hdr; int rcode = 0; + switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -296,6 +304,12 @@ boot_device = argv[2]; offset = simple_strtoul(argv[3], NULL, 16); break; + case 5: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + offset1 = simple_strtoul(argv[4], NULL, 16); + break; default: printf ("Usage:\n%s\n", cmdtp->usage); SHOW_BOOT_PROGRESS (-1); @@ -355,22 +369,28 @@ /* Check if we should attempt an auto-start */ if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; + char *local_args[3]; extern int do_bootm (cmd_tbl_t *, int, int, char *[]); local_args[0] = argv[0]; - local_args[1] = NULL; + local_args[1] = argv[1]; + local_args[2] = argv[4]; + local_args[3][0] = 'N'; + local_args[3][1] = (char *)NULL; printf ("Automatic boot of image at addr 0x%08lx ...\n", addr); - do_bootm (cmdtp, 0, 1, local_args); + if(offset1 == 0) + do_bootm (cmdtp, 0, 1, local_args); + else + do_bootm (cmdtp, 0, 4, local_args); rcode = 1; } return rcode; } U_BOOT_CMD( - nboot, 4, 1, do_nandboot, + nboot, 5, 1, do_nandboot, "nboot - boot from NAND device\n", "loadAddr dev\n" ); @@ -1000,6 +1020,16 @@ for (i = last; i < nand->oobblock; i++) nand->data_buf[i] = 0xff; +#ifdef CONFIG_SOCA7210 + { + unsigned char sum; + + for (i = 0,sum = 0; i < nand->oobblock; i++) + sum = sum + nand->data_buf[i]; + nand->data_buf[512] = sum & 0xff; + } +#endif + /* Send command to begin auto page programming */ NanD_Command(nand, NAND_CMD_READ0); NanD_Command(nand, NAND_CMD_SEQIN); @@ -1025,7 +1055,7 @@ printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page); return -1; } - + #ifdef CONFIG_MTD_NAND_VERIFY_WRITE /* * The NAND device assumes that it is always writing to @@ -1049,7 +1079,7 @@ /* Loop through and verify the data */ for (i = col; i < last; i++) { - if (nand->data_buf[i] != readb (nand->IO_ADDR)) { + if (nand->data_buf[i] != READ_NAND(nandptr)) { //readb (nand->IO_ADDR)) { printf ("%s: Failed write verify, page 0x%08x ", __FUNCTION__, page); return -1; } @@ -1063,7 +1093,7 @@ NanD_Command(nand, NAND_CMD_READOOB); NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col); for (i = 0; i < nand->oobsize; i++) - nand->data_buf[i] = readb (nand->IO_ADDR); + nand->data_buf[i] = READ_NAND(nandptr); //readb (nand->IO_ADDR); for (i = 0; i < ecc_bytes; i++) { if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { printf ("%s: Failed ECC write " @@ -1409,6 +1439,14 @@ { return 0; } +int readnand(size_t offset, size_t len, u_char * addr) +{ + if (nand_rw (nand_dev_desc, NANDRW_READ, offset, + len, NULL, (u_char *)addr)) { + printf ("** Read error on\n"); + } + return 1; +} unsigned long nand_probe(unsigned long physadr) { diff -urN u-boot-1.0.0/common/env_common.c u-boot-1.0.0-7210/common/env_common.c --- u-boot-1.0.0/common/env_common.c 2003-06-28 06:32:31.000000000 +0900 +++ u-boot-1.0.0-7210/common/env_common.c 2004-02-28 10:00:37.000000000 +0900 @@ -231,7 +231,7 @@ #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ puts ("Using default environment\n\n"); #else - puts ("*** Warning - bad CRC, using default environment\n\n"); +// puts ("*** Warning - bad CRC, using default environment\n\n"); SHOW_BOOT_PROGRESS (-1); #endif diff -urN u-boot-1.0.0/common/Makefile u-boot-1.0.0-7210/common/Makefile --- u-boot-1.0.0/common/Makefile 2003-10-10 05:09:04.000000000 +0900 +++ u-boot-1.0.0-7210/common/Makefile 2004-01-26 16:02:28.000000000 +0900 @@ -39,14 +39,13 @@ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \ - cmd_reginfo.o cmd_scsi.o cmd_spi.o cmd_usb.o cmd_vfd.o \ + cmd_reginfo.o cmd_spi.o cmd_usb.o cmd_vfd.o \ command.o console.o devices.o dlmalloc.o docecc.o \ environment.o env_common.o \ env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \ flash.o fpga.o \ - hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \ + hush.o kgdb.o lists.o miiphybb.o miiphyutil.o \ s_record.o soft_i2c.o soft_spi.o spartan2.o \ - usb.o usb_kbd.o usb_storage.o \ virtex2.o xilinx.o OBJS = $(AOBJS) $(COBJS) diff -urN u-boot-1.0.0/cpu/hms30c7210/config.mk u-boot-1.0.0-7210/cpu/hms30c7210/config.mk --- u-boot-1.0.0/cpu/hms30c7210/config.mk 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/config.mk 2003-11-28 17:43:36.000000000 +0900 @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -mshort-load-bytes -msoft-float + +PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi diff -urN u-boot-1.0.0/cpu/hms30c7210/cpu.c u-boot-1.0.0-7210/cpu/hms30c7210/cpu.c --- u-boot-1.0.0/cpu/hms30c7210/cpu.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/cpu.c 2004-01-26 11:23:42.000000000 +0900 @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1(void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + /* printf("p15/c1 is = %08lx\n", value); */ + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ + /* printf("write %08lx to p15/c1\n", value); */ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1(); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_IDC (1<<2) /* icache and/or dcache off/on */ +#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + +int cpu_init (void) +{ + /* + * setup up stack if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_end + \ + CONFIG_STACKSIZE + \ + CONFIG_STACKSIZE_IRQ - 4; + FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; + _armboot_real_end = FIQ_STACK_START + 4; +#else + _armboot_real_end = _armboot_end + CONFIG_STACKSIZE; +#endif + return (0); +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + * and we set the CPU-speed to 73 MHz - see start.S for details + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + +#ifdef CONFIG_ARM7_REVD + /* go to high speed */ +// IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; +#endif + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern void reset_cpu(ulong addr); + + disable_interrupts(); + reset_cpu(0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IDC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IDC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IDC) != 0; +} + +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IDC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IDC); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_IDC) != 0; +} diff -urN u-boot-1.0.0/cpu/hms30c7210/i2c.c u-boot-1.0.0-7210/cpu/hms30c7210/i2c.c --- u-boot-1.0.0/cpu/hms30c7210/i2c.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/i2c.c 2004-05-27 11:04:28.000000000 +0900 @@ -0,0 +1,358 @@ +/* + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_DRIVER_H7210_I2C + +#include +#include + +#ifdef CONFIG_HARD_I2C + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OK 0 +#define I2C_NOK 1 +#define I2C_NACK 2 +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ + +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ + +#define I2C_TIMEOUT 1 /* 1 second */ + + +static int GetI2CSDA(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + return (gpio->GPEDAT & 0x8000) >> 15; +#endif +#ifdef CONFIG_S3C2400 + return (gpio->PGDAT & 0x0020) >> 5; +#endif +} + +#if 0 +static void SetI2CSDA(int x) +{ + rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; +} +#endif + +static void SetI2CSCL(int x) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; +#endif +#ifdef CONFIG_S3C2400 + gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; +#endif +} + + +static int WaitForXfer (void) +{ + int i, status; + + i = I2C_TIMEOUT * 10000; + status = i2c->IICCON; + while ((i > 0) && !(status & I2CCON_IRPND)) { + udelay (100); + status = i2c->IICCON; + i--; + } + + return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; +} + +static int IsACK (void) +{ + return (!(i2c->IICSTAT & I2CSTAT_NACK)); +} + +static void ReadWriteByte (void) +{ + i2c->IICCON &= ~I2CCON_IRPND; +} + + +void i2c_init (int speed, int slaveadd) +{ + _outb(I2C_BAUDREG,speed); + _outb(I2C_SLAVEREG,slaveadd); +} + +/* + * cmd_type is 0 for write, 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + */ +static +int i2c_transfer (unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], unsigned short data_len) +{ + int i, status, result; + + if (data == 0 || data_len == 0) { + /*Don't support data transfer of no length or to address 0 */ + printf ("i2c_transfer: bad call\n"); + return I2C_NOK; + } + + /* Check I2C bus idle */ + i = I2C_TIMEOUT * 1000; + status = _inw(I2C_STATUSREG); + while ((i > 0) && (status & I2C_STATUSREG_BUSBUSY)) { + udelay (1000); + status = _inw(I2C_STATUSREG); + i--; + } + + if (status & I2C_STATUSREG_BUSBUSY) + return I2C_NOK_TOUT; + + result = I2C_OK; + + switch (cmd_type) { + case I2C_WRITE: + if (addr && addr_len) { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = addr[i]; + ReadWriteByte (); + i++; + } + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } else { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < data_len) && (result = I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } + + if (result == I2C_OK) + result = WaitForXfer (); + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + case I2C_READ: + if (addr && addr_len) { + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT |= I2C_START_STOP; + result = WaitForXfer (); + if (IsACK ()) { + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + i2c->IICDS = addr[i]; + ReadWriteByte (); + result = WaitForXfer (); + i++; + } + + i2c->IICDS = chip; + /* resend START */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP; + ReadWriteByte (); + result = WaitForXfer (); + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + + } else { + /* send START */ + _outb(I2C_TARGETREG,chip | I2C_TARGETREG_ADDR_READ); + _outb(I2C_CONFIGREG,I2C_CONFIGREG_SINGLEBYTE | I2C_CONFIGREG_MASTER); + + result = WaitForXfer (); + + if (IsACK ()) { + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + } + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + default: + printf ("i2c_transfer: bad call\n"); + result = I2C_NOK; + break; + } + + return (result); +} + +int i2c_probe (uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if (alen > 4) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if ((ret = + i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + printf ("I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if (alen > 4) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + return (i2c_transfer + (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, + len) != 0); +} +#endif /* CONFIG_HARD_I2C */ + +#endif /* CONFIG_DRIVER_H7210_I2C */ diff -urN u-boot-1.0.0/cpu/hms30c7210/interrupts.c u-boot-1.0.0-7210/cpu/hms30c7210/interrupts.c --- u-boot-1.0.0/cpu/hms30c7210/interrupts.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/interrupts.c 2004-01-26 16:29:22.000000000 +0900 @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +extern void reset_cpu(ulong addr); + +/* we always count down the max. */ +#define TIMER_LOAD_VAL 0xffff + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = + { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", + "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", + "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", + "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", + "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + /* disable all interrupts */ + _outw(INTC_ENABLE,0); + + /* operate timer 1 in prescale mode */ + _outw(TIMER_T1BASE,TIMER_LOAD_VAL); + _outw(TIMER_T1CTRL,TIMER_CTRL_RESET); + _outw(TIMER_T1CTRL,(TIMER_CTRL_REPEAT_MODE | TIMER_CTRL_COUNT_ENABLE)); + + /* enable Timer controller */ + _outw(TIMER_TOPCTRL,TIMER_TOCTRL_POWER_DOWN); + + lastdec = _inw(TIMER_T1COUNT); + + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + + if (usec < 1000){ + tmo = usec * CFG_HZ; + tmo /= 1000000; + } + else { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } + + tmo += get_timer (0); + + while (get_timer_masked () < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = _inw(TIMER_T1COUNT); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = _inw(TIMER_T1COUNT); + + if (now >= lastdec ) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + + if (usec < 1000){ + tmo = usec *CFG_HZ; + tmo /= 10000000; + } + else { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } + + reset_timer_masked (); + + while (get_timer_masked () < tmo) + /*NOP*/; +} diff -urN u-boot-1.0.0/cpu/hms30c7210/Makefile u-boot-1.0.0-7210/cpu/hms30c7210/Makefile --- u-boot-1.0.0/cpu/hms30c7210/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/Makefile 2004-05-24 13:42:30.000000000 +0900 @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o mmc.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff -urN u-boot-1.0.0/cpu/hms30c7210/mmc.c u-boot-1.0.0-7210/cpu/hms30c7210/mmc.c --- u-boot-1.0.0/cpu/hms30c7210/mmc.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/mmc.c 2004-05-24 13:31:43.000000000 +0900 @@ -0,0 +1,1037 @@ +/* + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "h7210mmc.h" +#ifdef CONFIG_MMC +//#define DEBUG_MSSG 1 + + +#define CSHIGH _outw(GPIO_EDATA,(_inw(GPIO_EDATA)|0x0004)) +#define CSLOW _outw(GPIO_EDATA,(_inw(GPIO_EDATA)&~0x0004)) + +#define BLOCKSIZE 512 +#define TIMEOUTWAITE 0x100 + + +volatile unsigned char MmcBuff[BLOCKSIZE+2]; +volatile unsigned short RxIndex; +volatile unsigned short TxIndex; +volatile unsigned short TotalCount; +volatile unsigned short ExtraToatl; +volatile unsigned char CMD_FORM_BYTE[6]; + + + + +//extern int fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +static block_dev_desc_t mmc_dev; + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *)&mmc_dev); +} + +/* + * FIXME needs to read cid and csd info to determine block size + * and other parameters + */ +static uchar mmc_buf[BLOCKSIZE]; +//static mmc_csd_t mmc_csd; +static int mmc_ready = 0; + +enum { + INT_NO, + INT_RORIS, + INT_TIS, + INT_TIS_DONE, + INT_RIS, + INT_RIS_DONE, + INT_FIFO + }; + +volatile int intstatus = INT_NO; + +void display_r1(unsigned char stat); +void display_r2(unsigned short stat); +void MAKE_CMD(unsigned char cmd, unsigned char arg1, unsigned char arg2, unsigned char arg3, unsigned char arg4) +{ CMD_FORM_BYTE[0] = (unsigned char)(0x40 | (cmd & 0x3f)); + CMD_FORM_BYTE[1] = (unsigned char)arg1; + CMD_FORM_BYTE[2] = (unsigned char)arg2; + CMD_FORM_BYTE[3] = (unsigned char)arg3; + CMD_FORM_BYTE[4] = (unsigned char)arg4; + CMD_FORM_BYTE[5] = (unsigned char)0xff; +} + +unsigned short calculate_dat_crc (unsigned char data[], unsigned data_length ) +{ + unsigned byte, bit; + unsigned reg; + + reg = 0l; + for (byte = 0; byte < data_length; byte++) + { + for (bit = 0; bit < 8; bit++) + { + reg <<= 1; + reg ^= (( ((data[byte] << (bit + (D_CRC_LEN - 7))) ^ reg) + & D_CRC_HIGHBIT) ? D_CRC_POLYN : 0); + } + } + + return (unsigned short)(reg & D_CRC_BITS); +} + +void append_cmd_crc(void) +{ + unsigned byte, bit; + unsigned char reg; + + reg = 0; + for (byte = 0; byte < 5; byte++){ + for (bit = 0; bit < 8; bit++){ + reg <<= 1; + reg ^= ((((CMD_FORM_BYTE[byte] << bit) ^ reg) & 0x80) ? 0x9 : 0); + } + } + CMD_FORM_BYTE[5] = (reg<<1) | 0x01; +} +unsigned power(unsigned i, unsigned k) +{ + if(k==0) return((unsigned)1); + else return(i*power(i, k-1)); +} + +unsigned long GetTotalSize(unsigned char *CSD) +{ + unsigned long i, multiplier, c_size, bl_len; + + c_size = ((*(CSD+6) & 0x03) << 10) + (*(CSD+7) << 2) + ((*(CSD+8) & 0xc0) >> 6); + i = ((*(CSD+9) & 0x03) <<1) + ((*(CSD+10) & 0x80)>>7); + multiplier = power(2,i+2); + bl_len = (*(CSD+5) & 0x0f); + + i = ((c_size+1)*multiplier) * power(2,bl_len); + +#ifdef DEBUG_MSSG + printf("This MMC Capacity is %d Mbytes.\n", i/power(1024,2)); +#endif + + return i; +} + + +static int Ssi0Handler(void) +{ + unsigned char status, i, tmp; + unsigned long delaycount=0; + + + do{ + status = _inb(SPI0_SSPIIR) & 0x07; + + if (status & SPI_SSPIIR_RORIS) { + intstatus = INT_RORIS; + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE); + _outb(SPI0_SSPICR,SPI_SSPIIR_RORIS); +#ifdef MSSG_ERR + printf( "SPI_SSPIIR_RORIS \n"); +#endif + return -1; + } + else if (status & SPI_SSPIIR_TIS){ + if(intstatus == INT_FIFO) + { + if(RxIndex < TotalCount) + { + for(i=0; i< 8; i++) + tmp = _inb(SPI0_SSPDR); + RxIndex += 8; + } + else + { + tmp = _inb(SPI0_SSPDR); + tmp = _inb(SPI0_SSPDR); + } + if(TxIndex < TotalCount) + { + for(i=0; i< 8; i++) + _outb(SPI0_SSPDR,*(MmcBuff+TxIndex++)); + } + else if(TxIndex == TotalCount) + { + _outb(SPI0_SSPIENT,0x2f); //TX 8 intr, RX NO + _outb(SPI0_SSPDR,*(MmcBuff+TxIndex++)); + _outb(SPI0_SSPDR,*(MmcBuff+TxIndex++)); + } + else + { + _outb(SPI0_SSPCR1,_inb(SPI0_SSPCR1) & ~SPI_SSPCR1_TIE); + _outb(SPI0_SSPICR,SPI_SSPIIR_TIS); + intstatus = INT_TIS_DONE; + // printf( "INT_TIS_DONE \n"); + return 0; + + } + _outb(SPI0_SSPICR,SPI_SSPIIR_TIS); + } + else + { + intstatus = INT_TIS; + _outb(SPI0_SSPCR1,_inb(SPI0_SSPCR1) & ~SPI_SSPCR1_TIE); + _outb(SPI0_SSPICR,SPI_SSPIIR_TIS); + return 0; + // printf( "INT_TIS \n"); + } + } + else if (status & SPI_SSPIIR_RIS){ + + if(intstatus == INT_FIFO) + { + if(RxIndex < TotalCount) + { + for(i=0; i<8;i++) + *(MmcBuff+RxIndex++) = _inb(SPI0_SSPDR); + if(RxIndex >= TotalCount) + _outb(SPI0_SSPIENT,0xf2); //TX NO intr, RX 2 + + } + else + { + *(MmcBuff+RxIndex++) = _inb(SPI0_SSPDR); + *(MmcBuff+RxIndex++) = _inb(SPI0_SSPDR); + } + if(RxIndex >= ExtraToatl) + { + _outb(SPI0_SSPCR1,_inb(SPI0_SSPCR1) & ~SPI_SSPCR1_RIE); + _outb(SPI0_SSPICR,SPI_SSPIIR_RIS); + intstatus = INT_RIS_DONE; + // printf( "INT_RIS_DONE \n"); + return 0; + } + + if(TxIndex < TotalCount) + { + for(i=0; i< 8; i++) + _outb(SPI0_SSPDR, 0xff); + TxIndex+= 8; + } + else if(TxIndex < ExtraToatl) + { + _outb(SPI0_SSPDR, 0xff); + _outb(SPI0_SSPDR, 0xff); + TxIndex += 2; + } + + _outb(SPI0_SSPICR,SPI_SSPIIR_RIS); + } + else + { + intstatus = INT_RIS; + _outb(SPI0_SSPCR1,_inb(SPI0_SSPCR1) & ~SPI_SSPCR1_RIE); + _outb(SPI0_SSPICR,SPI_SSPIIR_RIS); + return 0; + // printf( "INT_RIS \n"); + } + } + delaycount++; + }while(delaycount < 0xf00000); + return -1; +} + + + + +void spisendcommand(void) +{ + int i; + volatile unsigned char stat; + for (i=0;i<6;i++){ + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0x0f); + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_TIE); + _outb(SPI0_SSPDR,CMD_FORM_BYTE[i]); + if(Ssi0Handler() == -1) + { + printf( "semdcommand error \n"); + return; + } + stat =_inb(SPI0_SSPDR); + } +} + +void syncdevice(void) +{ + volatile unsigned char stat; + + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0x0f); //TX 1 over, RX NO intr + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_TIE); + _outb(SPI0_SSPDR,0xff); + if(Ssi0Handler() == -1) + { + printf( "syncdevice error\n"); + return; + } + + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0xf1); //TX NO intr, RX 1 + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_RIE); + if(Ssi0Handler() == -1) + { + printf( "syncdevice error\n"); + return; + } + stat =_inb(SPI0_SSPDR); +} + +unsigned char spigetchar(void) +{ + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0x0f); //TX 1 over, RX NO intr + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_TIE); + _outb(SPI0_SSPDR,0xff); + if(Ssi0Handler() == -1) + { + printf( "spigetchar error\n"); + return 0xff; + } + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0xf1); //TX NO intr, RX 1 + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_RIE); + if(Ssi0Handler() == -1) + { + printf( "spigetchar error\n"); + return 0xff; + } + + return _inb(SPI0_SSPDR); + +} +void spiputchar(unsigned char Ch) +{ + unsigned char stat; + + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0x0f); //TX 1 over, RX NO intr + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_TIE); + _outb(SPI0_SSPDR,Ch); + if(Ssi0Handler() == -1) + { + printf( "spiputchar error \n"); + return; + } + + intstatus = INT_NO; + _outb(SPI0_SSPIENT,0xf1); //TX NO intr, RX 1 + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_RIE); + if(Ssi0Handler() == -1) + { + printf( "spiputchar error \n"); + return; + } + stat =_inb(SPI0_SSPDR); +} + + + +int spimmc_SetBlkLen(void) +{ + int i; + volatile unsigned char stat; + unsigned int block_length; + // Send CMD16 Command - SET_BLOCKLEN + block_length = BLOCKSIZE; + MAKE_CMD(SET_BLOCKLEN,((block_length>>24)&0xff),((block_length>>16)&0xff),((block_length>>8)&0xff),(block_length&0xff)); + append_cmd_crc(); // Make CMD CRC +#ifdef DEBUG_MSSG + printf("SET_BLOCKLEN %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1],CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + syncdevice(); + syncdevice(); + spisendcommand(); + + // Receive Status + for (i=0;i<8;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) + break; + } + if (i==8) return -1; +#ifdef DEBUG_MSSG + printf("i=%d stat=%x \n",i,stat); +#endif + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + + return 0; +} + + +int spimmc_GetCSD(unsigned char *CSD) +{ + int i; + volatile unsigned char stat; + + // Send CMD9 Command - SEND_CSD + MAKE_CMD(SEND_CSD,0,0,0,0); + append_cmd_crc(); // Make CMD CRC +#ifdef DEBUG_MSSG + printf("SEND_CSD %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1], CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + syncdevice(); + syncdevice(); + spisendcommand(); + // Receive Status + + for (i=0;i<8;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) break; + } + + + if (i==8) return -1; +#ifdef DEBUG_MSSG + printf("%x \n",stat); +#endif + if (stat){ +#ifdef MSSG_ERR + printf("Get CSD error \n"); + display_r1(stat); +#endif + return -1; + } + + while(1){ + stat = spigetchar(); + if (stat != 0xff) { + if (stat == 0xfe) break; + else {printf("err2 ~0xfe\n"); return -1;} + } + } + _outb(SPI0_SSPCR1,0); + RxIndex = 0; + TotalCount = 16; + ExtraToatl = 18; + intstatus = INT_FIFO; + + _outb(SPI0_SSPIENT,0xf8); //TX NO intr, RX 8 + for(TxIndex=0; TxIndex< 8; TxIndex++) + _outb(SPI0_SSPDR, 0xff); + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_RIE);//|SPI_SSPCR1_TIE|SPI_SSPCR1_RIE); + if(Ssi0Handler() == -1) + { + printf( "spimmc_GetCSD error \n"); + return -1; + } + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + memcpy((char *)CSD, (char *)MmcBuff, 16); + return 0; +} + +int spimmc_reset(void) +{ + int i; + unsigned char stat; + +#ifdef DEBUG_MSSG + printf("spimmc_reset\n"); +#endif + + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + + CSHIGH; + for (i=0;i<10;i++){ + syncdevice(); + } + CSLOW; + + // Send CMD0 Command - go ilde state + MAKE_CMD(GO_IDLE_STATE,0,0,0,0); + append_cmd_crc(); // Make CMD CRC +#ifdef DEBUG_MSSG + printf("GO_IDLE_STATE %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1], CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + spisendcommand(); + // Receive Status + for (i=0;i<18;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) break; + } + + if (i==18) + { + printf("reset err\n"); + return -1; + } +#ifdef DEBUG_MSSG + printf("i=%d stat=%x \n",i,stat); +#endif + syncdevice(); + + // Send CMD1 Command - send op cond + MAKE_CMD(SEND_OP_COND,0,0,0,0); + append_cmd_crc(); // Make CMD CRC + while(1){ +#ifdef DEBUG_MSSG + printf("SEND_OP_COND %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1],CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + spisendcommand(); + // Receive Status + for (i=0;i<8;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) break; + } + if (i==8) return -1; + if (stat & IN_IDLE_STATE){ + syncdevice(); +#ifdef DEBUG_MSSG + printf("%x \n",stat); +#endif + } + else { +#ifdef DEBUG_MSSG + printf("Ok %x \n",stat); +#endif + return 0; + } + } +} + +int +/****************************************************/ +mmc_block_read(uchar *dst, ulong block_addr, ulong len) +/****************************************************/ +{ + int i; + unsigned char stat=0; + unsigned long delaycount; + +#ifdef DEBUG_MSSG + printf("READ_SINGLE_BLOCK\n"); +#endif + // Send CMD17 Command - READ_SINGLE_BLOCK + MAKE_CMD(READ_SINGLE_BLOCK,((block_addr>>24)&0xff),((block_addr>>16)&0xff),((block_addr>>8)&0xff),(block_addr&0xff)); + append_cmd_crc(); // Make CMD CRC +#ifdef DEBUG_MSSG + printf("READ_SINGLE_BLOCK %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1], CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + syncdevice(); + syncdevice(); + spisendcommand(); + // Receive Status + + for (i=0;i<8;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) break; + } + + if (i==8) goto ReadErr; +#ifdef DEBUG_MSSG + printf("%x \n",stat); +#endif + if (stat){ + +#ifdef MSSG_ERR + printf("Read error \n"); + display_r1(stat); +#endif + goto ReadErr; + } + + while(1){ + stat = spigetchar(); + if (stat != 0xff) { + if (stat == 0xfe) break; + else {printf("err3 ~0xfe\n");goto ReadErr;} + } + } + + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + RxIndex = 0; +// TxIndex = 0; + TotalCount = BLOCKSIZE; + ExtraToatl = BLOCKSIZE+2; + intstatus = INT_FIFO; + + _outb(SPI0_SSPIENT,0xf8); //TX NO intr, RX 8 + for(TxIndex=0; TxIndex< 8; TxIndex++) + _outb(SPI0_SSPDR, 0xff); + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_RIE);//|SPI_SSPCR1_TIE|SPI_SSPCR1_RIE); + if(Ssi0Handler() == -1) + { + printf( "mmc_block_read \n"); + goto ReadErr; + } + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + + // CSHIGH; + memcpy((char *)dst, (char *)MmcBuff, len); + return 0; + +ReadErr: + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + + delaycount=0; + while((spimmc_reset() == -1) && (delaycount < 10))delaycount++; + return -1; +} + + +int +/****************************************************/ +mmc_block_write(ulong block_addr, uchar *src, int len) +/****************************************************/ +{ + int i; + volatile unsigned char stat; + unsigned int delaycount; + unsigned short wCRC; +#ifdef DEBUG_MSSG + printf("WRITE_BLOCK\n"); +#endif + memcpy((char *)MmcBuff, (char *)src, len); + wCRC = calculate_dat_crc(MmcBuff, (unsigned)BLOCKSIZE); + + *(MmcBuff + BLOCKSIZE) = wCRC >> 8; + *(MmcBuff + BLOCKSIZE+1) = wCRC; + + + + // Send CMD24 Command - WRITE_BLOCK + MAKE_CMD(WRITE_BLOCK,((block_addr>>24)&0xff),((block_addr>>16)&0xff),((block_addr>>8)&0xff),(block_addr&0xff)); + append_cmd_crc(); // Make CMD CRC +#ifdef DEBUG_MSSG + printf("WRITE_BLOCK %x %x %x %x %x %x\n",CMD_FORM_BYTE[0],CMD_FORM_BYTE[1], CMD_FORM_BYTE[2],CMD_FORM_BYTE[3],CMD_FORM_BYTE[4],CMD_FORM_BYTE[5]); +#endif + syncdevice(); + syncdevice(); + syncdevice(); + spisendcommand(); + // Receive Status + for (i=0;i<8;i++){ + stat = spigetchar(); + if (!(stat& 0x80)) break; + } + + if (i==8) + { +#ifdef MSSG_ERR + printf(" i == 8 \n"); +#endif + goto WriteExit; + } + if (stat){ +#ifdef MSSG_ERR + printf("Write error \n"); + display_r1(stat); +#endif + goto WriteExit; + } + + spiputchar(0xFF); + spiputchar(0xFE); + + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + RxIndex = 0; + TxIndex = 0; + TotalCount = 512; + ExtraToatl = 514; + _outb(SPI0_SSPIENT,0x0f); //TX 8 intr, RX NO + intstatus = INT_FIFO; + for(i=0; i< 8; i++) + _outb(SPI0_SSPDR,*(MmcBuff+TxIndex++)); + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE|SPI_SSPCR1_TIE); + + if(Ssi0Handler() == -1) + { + printf("mmc_block_write\n"); + goto WriteExit; + } + + stat = spigetchar(); + if(stat == 0xE5) + { +#ifdef DEBUG_MSSG + printf("Status bits = 010 - Data accepted.\n"); +#endif + delaycount = 0; + do{ + stat = spigetchar(); + delaycount++; + } while(!stat && delaycount < 0x300); +#ifdef MSSG_ERR + if(delaycount >= 0x300) + printf("wrt busy.(0x%x)\n", stat); +#endif + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + return 0; + } + else if(stat == 0xEB) + { +#ifdef DEBUG_MSSG + printf("Status bits = 101 - Data rejected due to a CRC error.\n"); +#endif + + goto WriteExit; + } + else if(stat == 0xEE) + { +#ifdef DEBUG_MSSG + printf("Status bits = 110 - Data rejected due to a Write error.\n"); +#endif + + goto WriteExit; + } +WriteExit: + _outb(SPI0_SSPICR,(SPI_SSPIIR_RORIS|SPI_SSPIIR_TIS|SPI_SSPIIR_RIS)); + _outb(SPI0_SSPCR1,0); + + delaycount=0; + while((spimmc_reset() == -1) && (delaycount < 10))delaycount++; + return -1; + +} + + +int +/****************************************************/ +mmc_read(ulong src, uchar *dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) + { + return 0; + } + + if (!mmc_ready) + { + printf("Please initial the MMC first\n"); + return -1; + } + + mmc_block_size = BLOCKSIZE; + mmc_block_address = ~(mmc_block_size - 1); + + src -= CFG_MMC_BASE; + end = src + size; + part_start = ~mmc_block_address & src; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & src; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) + { + part_len = mmc_block_size - part_start; + printf("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) + { + return -1; + } + memcpy(dst, mmc_buf+part_start, part_len); + dst += part_len; + src += part_len; + } + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) + { + printf("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) + { + return -1; + } + } + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && src < end) + { + printf("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) + { + return -1; + } + memcpy(dst, mmc_buf, part_end); + } + return 0; +} + +int +/****************************************************/ +mmc_write(uchar *src, ulong dst, int size) +/****************************************************/ +{ + ulong end, part_start, part_end, part_len, aligned_start, aligned_end; + ulong mmc_block_size, mmc_block_address; + + if (size == 0) + { + return 0; + } + + if (!mmc_ready) + { + printf("Please initial the MMC first\n"); + return -1; + } + + mmc_block_size = BLOCKSIZE; + mmc_block_address = ~(mmc_block_size - 1); + + dst -= CFG_MMC_BASE; + end = dst + size; + part_start = ~mmc_block_address & dst; + part_end = ~mmc_block_address & end; + aligned_start = mmc_block_address & dst; + aligned_end = mmc_block_address & end; + + /* all block aligned accesses */ + + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_start) + { + part_len = mmc_block_size - part_start; + printf("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) + { + return -1; + } + memcpy(mmc_buf+part_start, src, part_len); + if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) + { + return -1; + } + dst += part_len; + src += part_len; + } + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) + { + printf("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) + { + return -1; + } + } + printf("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if (part_end && dst < end) + { + printf("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", + src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); + if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) + { + return -1; + } + memcpy(mmc_buf, src, part_end); + if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) + { + return -1; + } + } + return 0; +} + +ulong +/****************************************************/ +mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst) +/****************************************************/ +{ + int mmc_block_size = BLOCKSIZE; + ulong src = blknr * mmc_block_size + CFG_MMC_BASE; + mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); + return blkcnt; +} + + +int +/****************************************************/ +mmc_init(int verbose) +/****************************************************/ +{ + volatile unsigned char CSD128[16]; + + printf("MMC init start\n"); + + _outw(GPIO_EEN,_inw(GPIO_EEN)|0x0004); + _outw(GPIO_EDIR,_inw(GPIO_EDIR)&~0x0004); + _outw(GPIO_EDATA,_inw(GPIO_EDATA)|0x0004); + + _outdw((INTC_ENABLE), _indw(INTC_ENABLE) & ~0x2000000); + + // Initialize MMC Card - SPI Mode + _outb(SPI0_SSPCR0,(SPI_SSPCR0_GSEL | SPI_SSPCR0_SDIR)); + _outb(SPI0_SSPCSR,0x04); // (MAX.)35 MHz / 8 = 4.37MHz (SPI-MMC SpecMAX. 5Mhz Under) + _outb(SPI0_SSPCR1,SPI_SSPCR1_SSE);// SSI enable + + if( spimmc_reset() == -1) + { + if( spimmc_reset() == -1) + { + printf(" spimmc reset Error!\n"); + return -ENODEV; + } + } + + if (spimmc_SetBlkLen() == -1) + { + if (spimmc_SetBlkLen() == -1) + { + printf(" spimmc set Block len Error!\n"); + return -1; + } + } + + if(spimmc_GetCSD((unsigned char *)CSD128) == -1 ) + { + printf(" spimmc Get CSD Error!\n"); + return -ENODEV; + } + + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = GetTotalSize((unsigned char *)CSD128); + mmc_dev.lba >>= 9; + sprintf(mmc_dev.vendor,"Not Display"); + sprintf(mmc_dev.product,"Not Display"); + sprintf(mmc_dev.revision,"Not Display"); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + mmc_ready = 1; + + printf("MMC init ok\n"); + +// fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + return 0; +} + + + + +int +mmc_ident(block_dev_desc_t *dev) +{ + return 0; +} + +int +mmc2info(ulong addr) +{ + /* FIXME hard codes to 32 MB device */ + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) + { + printf(" mem ok\n"); + return 1; + } + return 0; +} + + +void display_r1(unsigned char stat) +{ + if (stat & 0x01) + printf("In Idle\n"); + if (stat & 0x02) + printf("Erase Reset\n"); + if (stat & 0x04) + printf("Illegel Command\n"); + if (stat & 0x08) + printf("COm CRC Error\n"); + if (stat & 0x10) + printf("Erase Sequence Error\n"); + if (stat & 0x20) + printf("Address Error\n"); + if (stat & 0x40) + printf("Param Error\n"); + +} + +void display_r2(unsigned short stat) +{ + if (stat & 0x01) + printf("Card is Locked\n"); + if (stat & 0x02) + printf("WP Erase Skip, Lock/Unlock CMD Failed\n"); + if (stat & 0x04) + printf("Error\n"); + if (stat & 0x08) + printf("CRC Error\n"); + if (stat & 0x10) + printf("Card ECC Failed\n"); + if (stat & 0x20) + printf("WP Violation\n"); + if (stat & 0x40) + printf("Erase Param\n"); + if (stat & 0x80) + printf("Out of Rang\n"); + + if (stat & 0x0100) + printf("In Idle\n"); + if (stat & 0x0200) + printf("Erase Reset\n"); + if (stat & 0x0400) + printf("Illegel Command\n"); + if (stat & 0x0800) + printf("COm CRC Error\n"); + if (stat & 0x1000) + printf("Erase Sequence Error\n"); + if (stat & 0x2000) + printf("Address Error\n"); + if (stat & 0x4000) + printf("Param Error\n"); + + +} + + +#endif diff -urN u-boot-1.0.0/cpu/hms30c7210/serial.c u-boot-1.0.0-7210/cpu/hms30c7210/serial.c --- u-boot-1.0.0/cpu/hms30c7210/serial.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/serial.c 2004-02-12 16:47:03.000000000 +0900 @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +void serial_putc (const char c); +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int reg = 0; + + if (gd->baudrate == 1200) + reg = 192; + else if (gd->baudrate == 9600) + reg = 24; + else if (gd->baudrate == 19200) + reg = 12; + else if (gd->baudrate == 38400) + reg = 6; + else if (gd->baudrate == 57600) + reg = 4; + else if (gd->baudrate == 115200) + reg = 2; + else + hang (); + +#if (CONFIG_SERIAL == 0) + _outb(UART0_UCR, UART_UCR_UARTEN); + _outb(UART0_LCR, UART_LCR_DLAB); + _outb(UART0_IER, 0x00); + _outb(UART0_DLL, reg); + _outb(UART0_DLM, 0x00); + _outb(UART0_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART0_FCR, UART_FCR_FIFO_EN); +#elif (CONFIG_SERIAL == 1) + _outb(UART1_UCR, UART_UCR_UARTEN); + _outb(UART1_LCR, UART_LCR_DLAB); + _outb(UART1_IER, 0x00); + _outb(UART1_DLL, reg); + _outb(UART1_DLM, 0x00); + _outb(UART1_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART1_FCR, UART_FCR_FIFO_EN); +#elif (CONFIG_SERIAL == 2) + _outb(UART2_UCR, UART_UCR_UARTEN); + _outb(UART2_LCR, UART_LCR_DLAB); + _outb(UART2_IER, 0x00); + _outb(UART2_DLL, reg); + _outb(UART2_DLM, 0x00); + _outb(UART2_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART2_FCR, UART_FCR_FIFO_EN); +#elif (CONFIG_SERIAL == 3) + _outb(UART3_UCR, UART_UCR_UARTEN); + _outb(UART3_LCR, UART_LCR_DLAB); + _outb(UART3_IER, 0x00); + _outb(UART3_DLL, reg); + _outb(UART3_DLM, 0x00); + _outb(UART3_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART3_FCR, UART_FCR_FIFO_EN); +#elif (CONFIG_SERIAL == 4) + _outb(UART4_UCR, UART_UCR_UARTEN); + _outb(UART4_LCR, UART_LCR_DLAB); + _outb(UART4_IER, 0x00); + _outb(UART4_DLL, reg); + _outb(UART4_DLM, 0x00); + _outb(UART4_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART4_FCR, UART_FCR_FIFO_EN); +#elif (CONFIG_SERIAL == 5) + _outb(UART5_UCR, UART_UCR_UARTEN); + _outb(UART5_LCR, UART_LCR_DLAB); + _outb(UART5_IER, 0x00); + _outb(UART5_DLL, reg); + _outb(UART5_DLM, 0x00); + _outb(UART5_LCR, (UART_LCR_NO_PARITY | UART_LCR_CHAR_LEN_8)); + _outb(UART5_FCR, UART_FCR_FIFO_EN); +#endif +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +#if (CONFIG_SERIAL == 0) + while (!(_inb(UART0_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART0_THR,c); + +#elif (CONFIG_SERIAL == 1) + while (!(_inb(UART1_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART1_THR,c); + +#elif (CONFIG_SERIAL == 2) + while (!(_inb(UART2_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART2_THR,c); + +#elif (CONFIG_SERIAL == 3) + while (!(_inb(UART3_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART3_THR,c); + +#elif (CONFIG_SERIAL == 4) + while (!(_inb(UART4_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART4_THR,c); + +#elif (CONFIG_SERIAL == 5) + while (!(_inb(UART5_LSR) & (UART_LSR_THRE|UART_LSR_TEMT))); + _outb(UART5_THR,c); +#endif +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +unsigned char UartTestFlag = 0; + +int serial_tstc (void) +{ + unsigned char stat; + +#if (CONFIG_SERIAL == 0) + stat = _inb(UART0_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART0_RBR); +#elif (CONFIG_SERIAL == 1) + stat = _inb(UART1_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART1_RBR); +#elif (CONFIG_SERIAL == 2) + stat = _inb(UART2_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART2_RBR); +#elif (CONFIG_SERIAL == 3) + stat = _inb(UART3_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART3_RBR); +#elif (CONFIG_SERIAL == 4) + stat = _inb(UART4_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART4_RBR); +#elif (CONFIG_SERIAL == 5) + stat = _inb(UART5_LSR); + if (stat & UART_LSR_DR){ + if (stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)){ + stat = _inb(UART5_RBR); +#endif + return (0); + } + else { + UartTestFlag = 0x01; + return (1); + } + } + else + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + unsigned char stat; + + if (UartTestFlag != 0){ + UartTestFlag = 0; +#if (CONFIG_SERIAL == 0) + return (_inb(UART0_RBR)); + } + else stat = _inb(UART0_LCR); + while (1){ + stat = _inb(UART0_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART0_RBR)); + +#elif (CONFIG_SERIAL == 1) + return (_inb(UART1_RBR)); + } + else stat = _inb(UART1_LCR); + while (1){ + stat = _inb(UART1_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART1_RBR)); + +#elif (CONFIG_SERIAL == 2) + return (_inb(UART2_RBR)); + } + else stat = _inb(UART2_LCR); + while (1){ + stat = _inb(UART2_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART2_RBR)); + +#elif (CONFIG_SERIAL == 3) + return (_inb(UART3_RBR)); + } + else stat = _inb(UART3_LCR); + while (1){ + stat = _inb(UART3_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART3_RBR)); + +#elif (CONFIG_SERIAL == 4) + return (_inb(UART4_RBR)); + } + else stat = _inb(UART4_LCR); + while (1){ + stat = _inb(UART4_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART4_RBR)); + +#elif (CONFIG_SERIAL == 5) + return (_inb(UART5_RBR)); + } + else stat = _inb(UART5_LCR); + while (1){ + stat = _inb(UART5_LSR); + if (stat & UART_LSR_DR){ + if (!(stat & (UART_LSR_FE|UART_LSR_PE|UART_LSR_OE))) break; + } + } + return (_inb(UART5_RBR)); +#endif +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff -urN u-boot-1.0.0/cpu/hms30c7210/start.S u-boot-1.0.0-7210/cpu/hms30c7210/start.S --- u-boot-1.0.0/cpu/hms30c7210/start.S 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/cpu/hms30c7210/start.S 2004-06-04 11:45:54.000000000 +0900 @@ -0,0 +1,441 @@ +/* + * armboot - Startup Code for ARM720 CPU-core + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * Note: _armboot_end_data and _armboot_end are defined + * by the (board-dependent) linker script. + * _armboot_end_data is the first usable FLASH address after armboot + */ +.globl _armboot_end_data +_armboot_end_data: + .word armboot_end_data +.globl _armboot_end +_armboot_end: + .word armboot_end + +/* + * _armboot_real_end is the first usable RAM address behind armboot + * and the various stacks + */ +.globl _armboot_real_end +_armboot_real_end: + .word 0x0badc0de + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0x13 + msr cpsr,r0 + +#ifdef CONFIG_SDRAM_START + b test_sdram +#endif + /* + * setting PMU default PMU[0x8001.0000] + */ + ldr r0,=0x80010000 + ldr r1,=0x10f + str r1, [r0, #0x20] + + /* + * setting PLL + */ + + ldr r1, [r0, #0x28] + bic r1, r1, #0xff /* bit clear */ + orr r1, r1, #0x32 /* 60 Mhz */ + str r1, [r0, #0x28] + + orr r1, r1, #0x40 /* FFREQ UPDATE CTRL 0-->1-->0 */ + str r1, [r0, #0x28] + and r1, r1, #0xbf + str r1, [r0, #0x28] + + /* + * goto RUN Mode + */ +/* + ldr r0,=0x80010000 + mov r1, #1 + str r1, [r0] +*/ + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifdef CONFIG_INIT_CRITICAL + bl cpu_init_crit +#endif + +relocate: + /* + * relocate armboot to RAM + */ + adr r0, _start /* r0 <- current position of code */ + ldr r2, _armboot_start + ldr r3, _armboot_end + sub r2, r3, r2 /* r2 <- size of armboot */ + ldr r1, _TEXT_BASE /* r1 <- destination address */ + add r2, r0, r2 /* r2 <- source end address */ + + /* + * r0 = source address + * r1 = target address + * r2 = source end address + */ + +copy_loop: + + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble copy_loop +/* + sub r2, r2, r0 +SDRAM_CODE_LOOP: + sub r2, r2, #0x4 + ldr r3, [r0] + str r3, [r1] + add r0, r0, #0x4 + add r1, r1, #0x4 + cmp r2, #0 + bge SDRAM_CODE_LOOP +*/ + + /* + * goto RUN Mode + */ + + ldr r0,=0x80010000 + mov r1, #1 + str r1, [r0] + +#ifdef CONFIG_SDRAM_START +test_sdram: +#endif + /* set up the stack */ + ldr r0, _armboot_end + add r0, r0, #CONFIG_STACKSIZE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15,0,r0,c1,c0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + mcr p15,0,r0,c1,c0 + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a memsetup.S in your board directory. + */ + mov ip, lr + bl memsetup + mov lr, ip + + mov pc, lr + + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + + ldr r2, _armboot_end + add r2, r2, #CONFIG_STACKSIZE + sub r2, r2, #8 + ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_end @ setup our mode stack + add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack + sub r13, r13, #8 + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + + .align 5 +.globl reset_cpu +reset_cpu: + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate cache + mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) + mrc p15, 0, ip, c1, c0, 0 @ get ctrl register + bic ip, ip, #0x000f @ ............wcam + bic ip, ip, #0x2100 @ ..v....s........ + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 diff -urN u-boot-1.0.0/drivers/cs8900.c u-boot-1.0.0-7210/drivers/cs8900.c --- u-boot-1.0.0/drivers/cs8900.c 2003-03-15 05:47:57.000000000 +0900 +++ u-boot-1.0.0-7210/drivers/cs8900.c 2004-04-27 14:01:29.000000000 +0900 @@ -105,13 +105,11 @@ unsigned char env_enetaddr[6]; char *tmp = getenv ("ethaddr"); char *end; - for (i=0; i<6; i++) { env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; if (tmp) tmp = (*end) ? end+1 : end; } - /* verify chip id */ if (get_reg_init_bus (PP_ChipID) != 0x630e) return; @@ -155,6 +153,7 @@ } } + } void eth_halt (void) @@ -168,9 +167,11 @@ int eth_init (bd_t * bd) { - + unsigned short chipid; + /* verify chip id */ - if (get_reg_init_bus (PP_ChipID) != 0x630e) { + if ((chipid =get_reg_init_bus (PP_ChipID)) != 0x630e) { + printf ("chipid [%x] \n",chipid); printf ("CS8900 Ethernet chip not found?!\n"); return 0; } diff -urN u-boot-1.0.0/include/configs/soca7210.h u-boot-1.0.0-7210/include/configs/soca7210.h --- u-boot-1.0.0/include/configs/soca7210.h 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/include/configs/soca7210.h 2004-06-04 11:49:47.000000000 +0900 @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the EP7312 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_SOCA7210 1 /* on an SOCA7210 Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 + +#define CONFIG_SDRAM_START +#undef CONFIG_SDRAM_START + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x02000300 +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL 2 /* we use Serial line 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 57600 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_DATE | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND ) + +#define CONFIG_RTC_H7210 1 + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "initrd root=/dev/ram console=ttyS2,57600" +#define CONFIG_ETHADDR //11:22:33:44:55:77 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.202.232 +#define CONFIG_SERVERIP 192.168.202.132 +#define CONFIG_BOOTFILE "soca7210" +#define CONFIG_BOOTCOMMAND "bootm 80000 200000" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 57600 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SOCA7210 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x40400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x42000000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00080000 /* default load address */ + +#define CFG_HZ 3686400 /* decrementer freq: 3.6864MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MBytes */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + + +#ifdef CONFIG_SDRAM_START +#define PHYS_FLASH_1 0x01000000 /*Flash Bank #1 */ +#else +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#endif + +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 2 +#define CFG_JFFS2_NUM_BANKS 1 + +/* +extern int smcebiconf_val; +*/ + +#define CFG_NAND_BASE ROM_CHIP_SELECT3 +#define NANDRB 0x0002 + +#define SMART_MEDIA_ALE 0x02 +#define SMART_MEDIA_CLE 0x01 + +/* NAND Flahs define */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_ENABLE_CE(nand) do {_outw(SMC_SMCEBICONF,(smcebiconf_val & ~SMC_SMCEBICONF_CE) );} while(0) +#define NAND_DISABLE_CE(nand) do {_outw(SMC_SMCEBICONF,(smcebiconf_val |SMC_SMCEBICONF_CE) );} while(0) +#define NAND_WAIT_READY(nand) while (!(_inw(GPIO_CDATA) & NANDRB)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +/* +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +*/ +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +/*********************************************************** + * I2C stuff: + * the SOCA7210 is equipped with an MICROCHIP 24LC256 EEPROM at + * address 0xA0 with 15bit addressing + ***********************************************************/ +//#define CONFIG_HARD_I2C /* I2C with hardware support */ +//#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +//#define CFG_I2C_SPEED 4 /* I2C speed [3.6864MHz/{2*(CFG_I2C_SPEED+1)}] = 368.64Khz*/ +//#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ + +//#define CFG_I2C_EEPROM_ADDR 0xA0 /* EEPROM address */ +//#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 1 address byte */ + +//#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +//#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */ +//#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + + +#endif /* __CONFIG_H */ diff -urN u-boot-1.0.0/include/h7210mmc.h u-boot-1.0.0-7210/include/h7210mmc.h --- u-boot-1.0.0/include/h7210mmc.h 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/include/h7210mmc.h 2004-05-22 10:38:40.000000000 +0900 @@ -0,0 +1,56 @@ +// MMC - SPI Command +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_XTER 12 +#define SEND_STATUS 13 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define WRITE_BLOCK 24 +#define CRC_ON_OFF 59 + +// MMC -SPI Response R1 +#define IN_IDLE_STATE (1 << 0) +#define ERASE_RESET (1 << 1) +#define ILLEGAL_COMMAND (1 << 2) +#define COM_CRC_ERROR (1 << 3) +#define ERASE_SEQ_ERROR (1 << 4) +#define ADDRESS_ERROR (1 << 5) +#define PARAMETER_ERROR (1 << 6) + +// MMC -SPI Response R1b +#define WP_ERASE_SKIP (1 << 1) +#define ERROR (1 << 2) +#define CC_ERROR (1 << 3) +#define CARD_ECC_FAILED (1 << 4) +#define WP_VIOLATION (1 << 5) +#define ERASE_PARAM (1 << 6) +#define OUT_OF_RANGE (1 << 7) + + +#define D_CRC_LEN 16 +#define D_CRC_POLYN 0x11021 +#define D_CRC_HIGHBIT 0x10000 +#define D_CRC_BITS 0x0FFFF + +#define _outb(a, v) (*(volatile unsigned char *)(a) = (v)) +#define _outw(a, v) (*(volatile unsigned short *)(a) = (v)) +#define _outdw(a, v) (*(volatile unsigned long *)(a) = (v)) + +#define _inb(a) (*(volatile unsigned char *)(a)) +#define _inw(a) (*(volatile unsigned short *)(a)) +#define _indw(a) (*(volatile unsigned long *)(a)) + +int spimmc_SendStatus(unsigned short *rep); +int spimmc_SetBlkLen(void); +int spimmc_GetCSD(unsigned char *CSD); +int spimmc_WriteBlock(unsigned long blkaddr, unsigned char * Data); +int spimmc_ReadBlock(unsigned long blkaddr, unsigned char *Data); +int spimmc_reset(void); +int spimmc_init(void); +unsigned long GetTotalSize(unsigned char *CSD); +int IsBusy(void); +void display_int(void); +//#define DEBUG_MSSG 1 +// #define MSSG_ERR 1 diff -urN u-boot-1.0.0/include/hms30c7210.h u-boot-1.0.0-7210/include/hms30c7210.h --- u-boot-1.0.0/include/hms30c7210.h 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/include/hms30c7210.h 2004-05-27 09:02:03.000000000 +0900 @@ -0,0 +1,1955 @@ +#ifndef _HMS30C7210_H +#define _HMS30C7210_H + +/* + HYNIX HMS30C7210 + 7210 Register Map +*/ +/* + 32 Bits Read/Write +*/ +#define _inw(addr) (*(volatile unsigned int *)(addr)) +#define _outw(addr, data) ((*(volatile unsigned int *)(addr)) = (data)) + +/* + 16 Bits Read/Write +*/ +#define _inh(addr) (*(volatile unsigned short *)(addr)) +#define _outh(addr, data) ((*(volatile unsigned short *)(addr)) = (data)) + +/* + 8 Bits Read/Write +*/ +#define _inb(addr) (*(volatile unsigned char *)(addr)) +#define _outb(addr, data) ((*(volatile unsigned char *)(addr)) = (data)) + +/* + Top-level address map +*/ +#define ROM_BASE 0x00000000 +#define ROM_SIZE 0x01000000 + +#define ROM_CHIP_SELECT0_OFFSET 0x00000000 +#define ROM_CHIP_SELECT1_OFFSET 0x01000000 +#define ROM_CHIP_SELECT2_OFFSET 0x02000000 +#define ROM_CHIP_SELECT3_OFFSET 0x03000000 + +#define ROM_CHIP_SELECT0 (ROM_BASE + ROM_CHIP_SELECT0_OFFSET) +#define ROM_CHIP_SELECT1 (ROM_BASE + ROM_CHIP_SELECT1_OFFSET) +#define ROM_CHIP_SELECT2 (ROM_BASE + ROM_CHIP_SELECT2_OFFSET) +#define ROM_CHIP_SELECT3 (ROM_BASE + ROM_CHIP_SELECT3_OFFSET) + +#define INTSRAM_BASE 0x3FFFE000 +#define INTSRAM_SIZE 0x2000 + +#define SDRAM_BASE 0x40000000 +#define SDRAM_SIZE 0x02000000 + +#define SDRAM_CHIP_SELECT0_OFFSET 0x00000000 +#define SDRAM_CHIP_SELECT1_OFFSET 0x02000000 +#define SDRAM_MODE_REG0_OFFSET 0x04000000 +#define SDRAM_MODE_REG1_OFFSET 0x06000000 + +#define SDRAM_CHIP_SELECT0 (SDRAM_BASE + SDRAM_CHIP_SELECT0_OFFSET) +#define SDRAM_CHIP_SELECT1 (SDRAM_BASE + SDRAM_CHIP_SELECT1_OFFSET) +#define SDRAM_MODE_REG0 (SDRAM_BASE + SDRAM_MODE_REG0_OFFSET) +#define SDRAM_MODE_REG1 (SDRAM_BASE + SDRAM_MODE_REG1_OFFSET) + + +/* + Peripherals Base Address Map + + ASB Peripherals +*/ +#define SDRAMC_BASE 0x80000000 // SDRAM CONTROLLER +#define PMU_BASE 0x80010000 // PMU +#define EXTFLASHC_BASE 0x80020000 // EXTERNAL BUS INTERFACE +#define INTSRAM_REG_BASE 0x80030000 // INTERNAL ROM REGISTER (TEST) +#define ARMTEST_BASE 0X80040000 // TO ARM CPU + +/* + ASB Peripherals +*/ +#define INTC_BASE 0x80050000 // INTERRUPT CONTROLLER +#define USB_BASE 0x80051000 // USB CONTROLLER +#define LCD_BASE 0x80052000 // LCD CONTROLLER +#define ADC_BASE 0x80053000 // ADC CONTROLLER +#define UART_BASE 0x80054000 // UART CONTROLLER +#define SPI_BASE 0x8005A000 // SPI CONTROLLER +#define SMC_BASE 0x8005C000 // SMC CONTROLLER +#define TIMER_BASE 0x8005D000 // TIME CONTROLLER +#define WDT_BASE 0x8005E000 // WDT CONTROLLER +#define RTC_BASE 0x8005F000 // RTC CONTROLLER +#define I2C_BASE 0x80060000 // I2C CONTROLLER +#define KBD_BASE 0x80061000 // KBD CONTROLLER +#define GPIO_BASE 0x80062000 // GPIO CONTROLLER + + +/* +// SDRAM CONTROLLER REGISTER +*/ +#define SDCON_OFFSET 0x00 +#define SDREF_OFFSET 0x04 +#define SDWBF_OFFSET 0x08 + +#define SDCON (SDRAMC_BASE + SDCON_OFFSET) // default: 0x00700000 +#define SDREF (SDRAMC_BASE + SDREF_OFFSET) // default: 0x0080 +#define SDWBF (SDRAMC_BASE + SDWBF_OFFSET) // default: 0x01 + +/* +// SDRAM Controller Configuration Register (SDCON) +// SDRAM Contoller configuration register bit assignment +*/ +/* + +----+----+-----+----+----+----+----+----+----+----+----+-----+----+----+-----+----+----+-----+ + | 31 | 30 | ... | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | ... | 7 | 6 | ... | 3 | 2 | ... | + +----+----+-----+----+----+----+----+----+----+----+----+-----+----+----+-----+----+----+-----+ + | S1 | S0 | ... | W | R | A | C1 | C0 | D | C | B | ... | E1 | B1 | ... | E0 | B0 | ... | + +----+----+-----+----+----+----+----+----+----+----+----+-----+----+----+-----+----+----+-----+ +*/ +#define SDCON_S1 (1 << 31) +#define SDCON_S0 (1 << 30) +#define SDCON_W (1 << 24) +#define SDCON_R (1 << 23) +#define SDCON_A (1 << 22) +#define SDCON_C1 (1 << 21) +#define SDCON_C0 (1 << 20) +#define SDCON_D (1 << 19) +#define SDCON_C (1 << 18) +#define SDCON_B (1 << 17) +#define SDCON_E1 (1 << 7) +#define SDCON_B1 (1 << 6) +#define SDCON_E0 (1 << 3) +#define SDCON_B0 (1 << 2) + +#define SDCON_SELF_REFRESH (2 << 30) // [S1..S0] b10: Self refresh +#define SDCON_BUSY (1 << 30) // [S1..S0] b01: Busy +#define SDCON_IDLE (0 << 30) // [S1..S0] b00: Idle + +#define SDCON_WAIT_DRIVER_ENABLE SDCON_W // [W] b1: Wait driver enable +#define SDCON_REFRESH_ENABLE SDCON_R // [R] b1: SDRAM controller provides refresh control +#define SDCON_AUTO_PRECHARGE SDCON_A // [A] b1: auto pre-charge (default) + +#define SDCON_CAS3 (3 << 20) // [C1..C0] b11: CAS latency3 +#define SDCON_CAS2 (2 << 20) // [C1..C0] b10: CAS latency2 +#define SDCON_CAS1 (1 << 20) // [C1..C0] b01: CAS latency1 + +#define SDCON_TRISTATE SDCON_D // [D] b1: SDRAM bus is tri-stated except during writes + // [D] b0: contrller drives the last data onto the SDRAM data bus (default) +#define SDCON_CLOCK_ENABLE SDCON_C // [C] : SDRAM Clock Enable Control +#define SDCON_WRITE_BUFFER_ENABLE SDCON_B // [B] b1: Write buffer enable + +#define SDRAM_NORMAL_CONTROL (SDCON_REFRESH_ENABLE | SDCON_CAS2 | SDCON_WRITE_BUFFER_ENABLE) +#define SDRAM_DEVICE0_ENABLE (SDCON_E0 | SDCON_B0) +#define SDRAM_DEVICE1_ENABLE (SDCON_E1 | SDCON_B1) + +/* +// SDRAM Controller Write buffer flush timer Register (SDWBF) +*/ +#define SDWBF_128 0x7 +#define SDWBF_64 0x6 +#define SDWBF_32 0x5 +#define SDWBF_16 0x4 +#define SDWBF_8 0x3 +#define SDWBF_4 0x2 +#define SDWBF_2 0x1 +#define SDWBF_TIME_OUT_DISABLE 0 + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// PMU CONTROLLER REGISTER +*/ +#define PMU_PMUMR_OFFSET 0 +#define PMU_PMUIDR_OFFSET 0x10 +#define PMU_PMURSR_OFFSET 0x20 +#define PMU_PMUCCR_OFFSET 0x28 +#define PMU_PMUDCTR_OFFSET 0x30 +#define PMU_PMUTR_OFFSET 0x38 + +#define PMU_PMUMR (PMU_BASE + PMU_PMUMR_OFFSET) // PMU Mode Register (0x8000.1000) +#define PMU_PMUIDR (PMU_BASE + PMU_PMUIDR_OFFSET) // PMU ID Register +#define PMU_PMURSR (PMU_BASE + PMU_PMURSR_OFFSET) // PMU Reset/Status Register +#define PMU_PMUCCR (PMU_BASE + PMU_PMUCCR_OFFSET) // PMU Clock Control Register (Default: 0x2F) +#define PMU_PMUDCTR (PMU_BASE + PMU_PMUDCTR_OFFSET) // PMU Debounce Counter Test Register +#define PMU_PMUTR (PMU_BASE + PMU_PMUTR_OFFSET) // PMU Test Register + +/* +// PMU Mode Register +*/ +#define PMU_PMUMR_INIT 0x04 // Initialization mode +#define PMU_PMUMR_RUN 0x01 // RUN mode +#define PMU_PMUMR_SLOW 0x00 // SLOW mode +#define PMU_PMUMR_IDLE 0x02 // IDLE mode +#define PMU_PMUMR_SLEEP 0x03 // SLEEP mode +#define PMU_PMUMR_DEEP_SLEEP 0x07 // DEEP SLEEP mode + +#define PMU_PMUMR_WAKEUP_CTRL 0x80 + +/* +// PMU Reset/Status Register +*/ +#define PMU_PMURSR_INTR_MASK 0xF800 // Interrupt Mask + +#define PMU_PMURSR_WARMRESET (1 << 26) // Software Warm Reset + +#define PMU_PMURSR_HOTSYNC_DBEN (1 << 25) // Debounce Enable of Hot Sync Event +#define PMU_PMURSR_WARM_RST_DBEN (1 << 24) // Debounce Enable of Warm Reset Event +#define PMU_PMURSR_PFAIL_DBEN (1 << 23) // Debounce Enable of Power Fail Event +#define PMU_PMURSR_MRING_DBEN (1 << 22) // Debounce Enable of Modem Ring Indicator Event +#define PMU_PMURSR_ONKEY_DBEN (1 << 21) // Debounce Enable of On Key Event + +#define PMU_PMURSR_HOTSYNC_WAKEN (1 << 20) // Wake-up Enable of Hot Sync Event +#define PMU_PMURSR_WARM_RST_WAKEN (1 << 19) // Wake-up Enable of External Warm Reset Event +#define PMU_PMURSR_RTC_WAKEN (1 << 18) // Wake-up Enable of RTC Alarm Event +#define PMU_PMURSR_MRING_WAKEN (1 << 17) // Wake-up Enable of Modem Ring Indicator Event +#define PMU_PMURSR_ONKEY_WAKEN (1 << 16) // Wake-up Enable of On Key Event + +#define PMU_PMURSR_HOTSYNC_INTREN (1 << 15) // Interrupt Mask of HOT SYNC Event +#define PMU_PMURSR_PFAIL_INTREN (1 << 14) // Interrupt Mask of Power Fail Event +#define PMU_PMURSR_RTC_INTREN (1 << 13) // Interrupt Mask of RTC Alarm Event +#define PMU_PMURSR_MRING_INTREN (1 << 12) // Interrupt Mask of Modem Ring Indicator Event +#define PMU_PMURSR_ONKEY_INTREN (1 << 11) // Interrupt Mask of On Key Event + +#define PMU_PMURSR_HOTSYNC_EVT (1 << 10) // Hot Sync Event +#define PMU_PMURSR_WDT_RST_EVT (1 << 9) // Watch Dog Timer Reset Event +#define PMU_PMURSR_WARM_RST_EVT (1 << 8) // Warm Reset Event +#define PMU_PMURSR_PFAIL_EVT (1 << 7) // Power Fail Event +#define PMU_PMURSR_RTC_EVT (1 << 6) // RTC Alarm Event +#define PMU_PMURSR_MRING_EVT (1 << 5) // Modem Ring Indicator Event +#define PMU_PMURSR_ONKEY_EVT (1 << 4) // On Key Event + +#define PMU_PMURSR_FPLL_LOCK (1 << 3) // FCLK PLL Lock Event +#define PMU_PMURSR_CPLL_LOCK (1 << 2) // CCLK PLL Lock Event +#define PMU_PMURSR_POR_EVT (1 << 0) // POR Event + +/* +// PMU Clock Control Register +*/ +#define PMU_PMUCCR_PLL_MASK 0x00FF // PMU PLL Mask +#define PMU_PMUCCR_PLL_FREQ_MASK 0x003F // PLL Frequency Mask + +#define PMU_PMUCCR_CCLK_ENABLE (1 << 15) // CCLK enable +#define PMU_PMUCCR_VCLK_ENABLE (1 << 14) // VCLK enable +#define PMU_PMUCCR_VCLK_SEL (1 << 13) // VCLK select 1:CCLK, 0:FCLK + +#define PMU_PMUCCR_FCLK_MUTE (1 << 7) // set: FCLK only muted after nPOR or nRESET +#define PMU_PMUCCR_FCLK_FREQ_UPDATE (1 << 6) // set: FCLK Frequency control is update instantaneously + +#define PMU_PMUCCR_FCLK_FREQ_UPDATE_MASK PMU_PMUCCR_FCLK_FREQ_UPDATE + +#define PMU_PMUCCR_40_5M 0x19 +#define PMU_PMUCCR_42M 0x1A +#define PMU_PMUCCR_43_5M 0x1B +#define PMU_PMUCCR_45M 0x1C +#define PMU_PMUCCR_46_5M 0x1D +#define PMU_PMUCCR_48M 0x1E +#define PMU_PMUCCR_42MHZ 0x2C +#define PMU_PMUCCR_45MHZ 0x2D +#define PMU_PMUCCR_48MHZ 0x2E +#define PMU_PMUCCR_51MHZ 0x2F +#define PMU_PMUCCR_54MHZ 0x30 +#define PMU_PMUCCR_57MHZ 0x31 +#define PMU_PMUCCR_60MHZ 0x32 +#define PMU_PMUCCR_63MHZ 0x33 +#define PMU_PMUCCR_66MHZ 0x34 +#define PMU_PMUCCR_69MHZ 0x35 +#define PMU_PMUCCR_72MHZ 0x36 +#define PMU_PMUCCR_75MHZ 0x37 +#define PMU_PMUCCR_78MHZ 0x38 +#define PMU_PMUCCR_81MHZ 0x39 +#define PMU_PMUCCR_84MHZ 0x3A +#define PMU_PMUCCR_87MHZ 0x3B +#define PMU_PMUCCR_90MHZ 0x3C +#define PMU_PMUCCR_93MHZ 0x3D +#define PMU_PMUCCR_96MHZ 0x3E + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// STATIC MEMORY INTERFACE +*/ +#define GCTRL_REG_OFFSET 0x00 +#define BANK0_REG_OFFSET 0x04 +#define BANK1_REG_OFFSET 0x08 +#define BANK2_REG_OFFSET 0x0c +#define BANK3_REG_OFFSET 0x10 + +#define GCTRL_REG (EXTFLASHC_BASE + GCTRL_REG_OFFSET) +#define BANK0_REG (EXTFLASHC_BASE + BANK0_REG_OFFSET) +#define BANK1_REG (EXTFLASHC_BASE + BANK1_REG_OFFSET) +#define BANK2_REG (EXTFLASHC_BASE + BANK2_REG_OFFSET) +#define BANK3_REG (EXTFLASHC_BASE + BANK3_REG_OFFSET) + +/* +// MEM Configuration (MEMCFG) Register +*/ +#define MEMCFG_BT_DONE (1 << 12) +#define MEMCFG_BUR_EN_MASK 0x0800 +#define MEMCFG_BUR_EN (1 << 11) + +#define MEMCFG_BURST_READ_WAIT_STATE_MASK 0x0780 +#define MEMCFG_BURST_REAS_WAIT_STATE_0 (0 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_1 (1 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_2 (2 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_3 (3 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_4 (4 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_5 (5 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_6 (6 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_7 (7 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_8 (8 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_9 (9 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_10 (10 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_11 (11 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_12 (12 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_13 (13 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_14 (14 << 7) +#define MEMCFG_BURST_REAS_WAIT_STATE_15 (15 << 7) // default + +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_MASK 0x0078 +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_1 (0 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_2 (1 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_3 (2 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_4 (3 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_5 (4 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_6 (5 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_7 (6 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_8 (7 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_9 (8 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_10 (9 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_11 (10 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_12 (11 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_13 (12 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_14 (13 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_15 (14 << 3) +#define MEMCFG_NORMAL_ACCESS_WAIT_STATE_16 (15 << 3) // default + +#define MEMCFG_MEM_WIDTH_MASK 0x0003 // Memory Width Mask +#define MEMCFG_MEM_WIDTH_16 (1 << 0) // 16 bit Memory Width +#define MEMCFG_MEM_WIDTH_8 (0 << 0) // 8 bit Memory Width + +#define MEMCFG_BOOT_SEL_MASK 0x0003 +#define MEMCFG_BOOT_SEL_SMC (1 << 0) +#define MEMCFG_BOOT_SEL_MMC (0 << 0) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// Internal SRAM Register +*/ +#define INTSRAM_RER_OFFSET 0 +#define INTSRAM_RSAR_OFFSET 0x08 + +#define INTSRAM_RER (INTSRAM_REG_BASE + INTSRAM_RER_OFFSET) // Internal SRAM Remapping Enable Register +#define INTSRAM_RSAR (INTSRAM_REG_BASE + INTSRAM_RSAR_OFFSET)// Internal SRAM Remap Source Address Register + +#define INTSRAM_RER_REMAP_SIZE_MASK 0x00001FF8 // Remapping Enable Register Mask +#define INTSRAM_RER_REMAP_EN (1 << 0) // b1: Enable Remap + +#define INTSRAM_RSAR_REMAP_SOURCE_ADDRESS_MASK 0x01FFFFFC // Remap Source Address + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// Interrupt Controller Registers +*/ +#define ENABLE_OFFSET 0 +#define DIR_OFFSET 0x04 +#define STATUS_OFFSET 0x08 +#define IRQFIQ_OFFSET 0x20 + + +#define INTC_ENABLE (INTC_BASE + ENABLE_OFFSET) +#define INTC_DIR (INTC_BASE + DIR_OFFSET) +#define INTC_STATUS (INTC_BASE + STATUS_OFFSET) +#define INTC_IRQFIQ (INTC_BASE + IRQFIQ_OFFSET) + +#define INT_PMU 0 +#define INT_USB 1 +#define INT_LCD 2 +#define INT_ADC 3 +#define INT_UART0 4 +#define INT_UART1 5 +#define INT_UART2 6 +#define INT_UART3 7 +#define INT_UART4 8 +#define INT_UART5 9 +#define INT_SPI0 10 +#define INT_SPI1 11 +#define INT_SMC 12 +#define INT_TIMER0 13 +#define INT_TIMER1 14 +#define INT_TIMER2 15 +#define INT_TIMER3 16 +#define INT_WDT 17 +#define INT_RTC 18 +#define INT_I2C 19 +#define INT_KBD 20 +#define INT_GPIOA 21 +#define INT_GPIOB 22 +#define INT_GPIOC 23 +#define INT_GPIOD 24 +#define INT_GPIOE 25 +#define INT_EXT0 26 +#define INT_EXT1 27 +#define INT_TICK 28 + +#define INTC_DIR_PMU (1 << 0) +#define INTC_DIR_USB (1 << 1) +#define INTC_DIR_LCD (1 << 2) +#define INTC_DIR_ADC (1 << 3) +#define INTC_DIR_UART0 (1 << 4) +#define INTC_DIR_UART1 (1 << 5) +#define INTC_DIR_UART2 (1 << 6) +#define INTC_DIR_UART3 (1 << 7) +#define INTC_DIR_UART4 (1 << 8) +#define INTC_DIR_UART5 (1 << 9) +#define INTC_DIR_SPI0 (1 << 10) +#define INTC_DIR_SPI1 (1 << 11) +#define INTC_DIR_SMC (1 << 12) +#define INTC_DIR_TIMER0 (1 << 13) +#define INTC_DIR_TIMER1 (1 << 14) +#define INTC_DIR_TIMER2 (1 << 15) +#define INTC_DIR_TIMER3 (1 << 16) +#define INTC_DIR_WDT (1 << 17) +#define INTC_DIR_RTC (1 << 18) +#define INTC_DIR_I2C (1 << 19) +#define INTC_DIR_KBD (1 << 20) +#define INTC_DIR_GPIOA (1 << 21) +#define INTC_DIR_GPIOB (1 << 22) +#define INTC_DIR_GPIOC (1 << 23) +#define INTC_DIR_GPIOD (1 << 24) +#define INTC_DIR_GPIOE (1 << 25) +#define INTC_DIR_EXT0 (1 << 26) +#define INTC_DIR_EXT1 (1 << 27) +#define INTC_DIR_TICK (1 << 28) +#define INTC_DIR_EXT3 (1 << 29) + +#define INTC_STATUS_PMU (1 << 0) +#define INTC_STATUS_USB (1 << 1) +#define INTC_STATUS_LCD (1 << 2) +#define INTC_STATUS_ADC (1 << 3) +#define INTC_STATUS_UART0 (1 << 4) +#define INTC_STATUS_UART1 (1 << 5) +#define INTC_STATUS_UART2 (1 << 6) +#define INTC_STATUS_UART3 (1 << 7) +#define INTC_STATUS_UART4 (1 << 8) +#define INTC_STATUS_UART5 (1 << 9) +#define INTC_STATUS_SPI0 (1 << 10) +#define INTC_STATUS_SPI1 (1 << 11) +#define INTC_STATUS_SMC (1 << 12) +#define INTC_STATUS_TIMER0 (1 << 13) +#define INTC_STATUS_TIMER1 (1 << 14) +#define INTC_STATUS_TIMER2 (1 << 15) +#define INTC_STATUS_TIMER3 (1 << 16) +#define INTC_STATUS_WDT (1 << 17) +#define INTC_STATUS_RTC (1 << 18) +#define INTC_STATUS_I2C (1 << 19) +#define INTC_STATUS_KBD (1 << 20) +#define INTC_STATUS_GPIOA (1 << 21) +#define INTC_STATUS_GPIOB (1 << 22) +#define INTC_STATUS_GPIOC (1 << 23) +#define INTC_STATUS_GPIOD (1 << 24) +#define INTC_STATUS_GPIOE (1 << 25) +#define INTC_STATUS_EXT0 (1 << 26) +#define INTC_STATUS_EXT1 (1 << 27) +#define INTC_STATUS_TICK (1 << 28) +#define INTC_STATUS_EXT3 (1 << 29) (1 << 30) + +#define INTC_IRQFIQ_FIQ (1 << 0) +#define INTC_IRQFIQ_IRQ (1 << 1) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// USB Controller Registers +*/ +#define USB_GCTRL_OFFSET 0 +#define USB_EPCTRL_OFFSET 0x04 +#define USB_INTMASK_OFFSET 0x08 +#define USB_INTSTAT_OFFSET 0x0C +#define USB_PWR_OFFSET 0x10 +#define USB_DEVID_OFFSET 0x18 +#define USB_DEVCLASS_OFFSET 0x1C +#define USB_INTCLASS_OFFSET 0x20 +#define USB_SETUP0_OFFSET 0x24 +#define USB_SETUP1_OFFSET 0x28 +#define USB_ENDP0RD_OFFSET 0x2C +#define USB_ENDP0WT_OFFSET 0x30 +#define USB_ENDP1RD_OFFSET 0x34 +#define USB_ENDP2WT_OFFSET 0x38 + +#define USB_GCTRL (USB_BASE + USB_GCTRL_OFFSET) +#define USB_EPCTRL (USB_BASE + USB_EPCTRL_OFFSET) +#define USB_INTMASK (USB_BASE + USB_INTMASK_OFFSET) +#define USB_INTSTAT (USB_BASE + USB_INTSTAT_OFFSET) +#define USB_PWR (USB_BASE + USB_PWR_OFFSET) +#define USB_DEVID (USB_BASE + USB_DEVID_OFFSET) +#define USB_DEVCLASS (USB_BASE + USB_DEVCLASS_OFFSET) +#define USB_INTCLASS (USB_BASE + USB_INTCLASS_OFFSET) +#define USB_SETUP0 (USB_BASE + USB_SETUP0_OFFSET) +#define USB_SETUP1 (USB_BASE + USB_SETUP1_OFFSET) +#define USB_ENDP0RD (USB_BASE + USB_ENDP0RD_OFFSET) +#define USB_ENDP0WT (USB_BASE + USB_ENDP0WT_OFFSET) +#define USB_ENDP1RD (USB_BASE + USB_ENDP1RD_OFFSET) +#define USB_ENDP2WT (USB_BASE + USB_ENDP2WT_OFFSET) + +/* +// GCTRL +*/ +#define USB_GTRL_MASK 0x0F +#define USB_GTRL_TRANDIS (1 << 3) +#define USB_GTRL_WBACK (1 << 2) +#define USB_GTRL_RESUME (1 << 1) +#define USB_GTRL_DMADIS (1 << 0) + +/* +// EPCTRL +*/ +#define USB_EPCTRL_MASK 0x001FFFFF +#define USB_EPCTRL_CLR2 (1 << 20) +#define USB_EPCTRL_CLR1 (1 << 19) +#define USB_EPCTRL_CLR0 (1 << 18) +#define USB_EPCTRL_E2TXB_MASK 0x0003FFFF +#define USB_EPCTRL_E2TXB_0 (0 << 16) +#define USB_EPCTRL_E2TXB_1 (1 << 16) +#define USB_EPCTRL_E2TXB_2 (2 << 16) +#define USB_EPCTRL_E2TXB_3 (3 << 16) +#define USB_EPCTRL_E2SND (1 << 15) +#define USB_EPCTRL_E2NK (1 << 14) +#define USB_EPCTRL_E2ST (1 << 13) +#define USB_EPCTRL_E2EN (1 << 12) +#define USB_EPCTRL_E1RCV (1 << 11) +#define USB_EPCTRL_E1NK (1 << 10) +#define USB_EPCTRL_E1ST (1 << 9) +#define USB_EPCTRL_E1EN (1 << 8) +#define USB_EPCTRL_E0TXB_MASK 0x000000F0 +#define USB_EPCTRL_E0TXB_3 (1 << 7) +#define USB_EPCTRL_E0TXB_2 (1 << 6) +#define USB_EPCTRL_E0TXB_1 (1 << 5) +#define USB_EPCTRL_E0TXB_0 (1 << 4) +#define USB_EPCTRL_E0NK (1 << 3) +#define USB_EPCTRL_E0ST (1 << 2) +#define USB_EPCTRL_E0TR (1 << 1) +#define USB_EPCTRL_E0EN (1 << 0) + +/* +// INTMASK +*/ +#define USB_INTMASK_MASK 0x000003FF +#define USB_INTMASK_E0STL (1 << 9) +#define USB_INTMASK_SUS (1 << 8) +#define USB_INTMASK_RESET (1 << 7) +#define USB_INTMASK_E2EM (1 << 6) +#define USB_INTMASK_E1OV (1 << 5) +#define USB_INTMASK_E1FU (1 << 4) +#define USB_INTMASK_E0EM (1 << 3) +#define USB_INTMASK_E0OV (1 << 2) +#define USB_INTMASK_E0FU (1 << 1) +#define USB_INTMASK_SET (1 << 0) + +/* +// INTSTAT +*/ +#define USB_INTSTAT_MASK 0x000FFFFF +#define USB_INTSTAT_EP2RXBYTE_MASK 0x000FC000 +#define USB_INTSTAT_EP0RXBYTE_MASK 0x00003C00 +#define USB_INTSTAT_E0STL (1 << 9) +#define USB_INTSTAT_SUS (1 << 8) +#define USB_INTSTAT_RESET (1 << 7) +#define USB_INTSTAT_E2EM (1 << 6) +#define USB_INTSTAT_E1OV (1 << 5) +#define USB_INTSTAT_E1FU (1 << 4) +#define USB_INTSTAT_E0EM (1 << 3) +#define USB_INTSTAT_E0OV (1 << 2) +#define USB_INTSTAT_E0FU (1 << 1) +#define USB_INTSTAT_SET (1 << 0) + +/* +// PWR +*/ +#define USB_PWR_EN_BCLK (1 << 3) +#define USB_PWR_SWUPDATE (1 << 2) +#define USB_PWR_PWR_MD_MASK 0x00000003 +#define USB_PWR_PWR_MD_FULL_POWER_DOWN 0 +#define USB_PWR_PWR_MD_POWER_DOWN 1 +#define USB_PWR_PWR_MD_FULL_POWER_OPERATION 2 + + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// LCD Controller Registers +*/ +#define LCD_CONTROL_OFFSET 0 +#define LCD_STATUS_OFFSET 0x0004 +#define LCD_STATUS_M_OFFSET 0x0008 +#define LCD_INTERRUPT_OFFSET 0x000C +#define LCD_DBAR_OFFSET 0x0010 +#define LCD_DCAR_OFFSET 0x0014 +#define LCD_TIMING_0_OFFSET 0x0020 +#define LCD_TIMING_1_OFFSET 0x0024 +#define LCD_TIMING_2_OFFSET 0x0028 +#define LCD_PALETTER_OFFSET 0x0030 +#define LCD_PALETTEG_OFFSET 0x0034 +#define LCD_PALETTEB_OFFSET 0x0038 + +#define LCD_CONTROL (LCD_BASE + LCD_CONTROL_OFFSET) // LCD Control Register +#define LCD_STATUS (LCD_BASE + LCD_STATUS_OFFSET) // LCD Status Register +#define LCD_STATUS_M (LCD_BASE + LCD_STATUS_M_OFFSET) // LCD Status Mask Register +#define LCD_INTERRUPT (LCD_BASE + LCD_INTERRUPT_OFFSET) // LCD Interrupt Register +#define LCD_DBAR (LCD_BASE + LCD_DBAR_OFFSET) // LCD DMA Channel Base Address Register +#define LCD_DCAR (LCD_BASE + LCD_DCAR_OFFSET) // LCD DMA Channel Current Address Register +#define LCD_TIMING_0 (LCD_BASE + LCD_TIMING_0_OFFSET) // LCD Timing 0 Register +#define LCD_TIMING_1 (LCD_BASE + LCD_TIMING_1_OFFSET) // LCD Timing 1 Register +#define LCD_TIMING_2 (LCD_BASE + LCD_TIMING_2_OFFSET) // LCD Timing 2 Register +#define LCD_PALETTER (LCD_BASE + LCD_PALETTER_OFFSET) // LCD Palette for Red Color or LSW of Gray +#define LCD_PALETTEG (LCD_BASE + LCD_PALETTEG_OFFSET) // LCD Palette for Green Color or MSW of Gray +#define LCD_PALETTEB (LCD_BASE + LCD_PALETTEB_OFFSET) // LCD Palette for Blue Color + +/* +// LCD Power Control +*/ + +#define LCD_CONTROL_RESET (1 << 31) +#define LCD_CONTROL_LCD_VCOMP_MASK 0x00003000 // Generate interrupt Mask +#define LCD_CONTROL_LCD_VCOMP (0 << 12) +#define LCD_CONTROL_LCD_BACKPORCH (1 << 12) +#define LCD_CONTROL_LCD_ACTIVEVIDEO (2 << 12) +#define LCD_CONTROL_LCD_FRONTPORCH (3 << 12) + +#define LCD_CONTROL_LCD_BEP (1 << 10) // LCD Big Endian +#define LCD_CONTROL_LCD_BPP_1BPP (0 << 8) // 1bpp +#define LCD_CONTROL_LCD_BPP_2BPP (1 << 8) // 2bpp +#define LCD_CONTROL_LCD_BPP_4BPP (2 << 8) // 4bpp +#define LCD_CONTROL_LCD_BPP_8BPP (3 << 8) // 8bpp + +#define LCD_CONTROL_BGR (1 << 6) // b1: BGR red and blue swapped for LCD +#define LCD_CONTROL_LCD_MONO_8 (1 << 5) // LCD monochrome data width. b0: 4 bits, b1: 8 bits +#define LCD_CONTROL_LCD_BW (1 << 4) // LCD Monochrome. b0: Color, b1: Mono +#define LCD_CONTROL_LCD_BLE (1 << 2) // LCD Backlight enable +#define LCD_CONTROL_LCD_PWR (1 << 1) // LCD power enable +#define LCD_CONTROL_LCD_EN (1 << 0) // LCD Controller Enable + +/* +// LCD Controller Status/Mask and Interrupt Register +*/ +#define LCD_STATUS_LDONE (1 << 3) // LCD Done frame status bit +#define LCD_STATUS_VCOMP (1 << 2) // Vertical compare interrupt +#define LCD_STATUS_LNEXT (1 << 1) // LCD Next base address update status bit +#define LCD_STATUS_LFUF (1 << 0) // FIFO underflow status bit + +#define LCD_STATUS_M_LDONE (1 << 3) // LCD Done frame mask bit +#define LCD_STATUS_M_VCOMP (1 << 2) // Vertical compare interrupt +#define LCD_STATUS_M_LNEXT (1 << 1) // LCD Next base address update amsk bit +#define LCD_STATUS_M_LFUF (1 << 0) // FIFO underflow mask bit + +#define LCD_INTERRUPT_LDONE (1 << 3) // LCD Done frame interrupt bit +#define LCD_INTERRUPT_VCOMP (1 << 2) // Vertical compare interrupt +#define LCD_INTERRUPT_LNEXT (1 << 1) // LCD Next base address update interrupt bit +#define LCD_INTERRUPT_LFUF (1 << 0) // FIFO underflow interrupt bit + +/* +// LCD DMA Base Address Register (DBAR) +*/ +#define LCD_DBAR_MASK 0x7fffffc0 + +/* +// LCD DMA Channel Current Address Register (DCAR) +*/ +#define LCD_DCAR_MASK 0x7fffffc0 + +/* +// LCD Timing 0 Register (TIMING_0) +*/ +#define LCD_TIMING_0_HBP_MASK 0xFF000000 // Horizontal Back Porch +#define LCD_TIMING_0_HFP_MASK 0x00FF0000 // Horizontal Front Porch +#define LCD_TIMING_0_HSW_MASK 0x0000FF00 // Horizontal Sync Pulse Width +#define LCD_TIMING_0_PPL_MASK 0x0000007F // Pixels-per-line (PPL) bit-field + +/* +// LCD Timing 1 Register (TIMING_1) +*/ +#define LCD_TIMING_1_VBP_MASK 0xFF000000 // Vertical Back Porch +#define LCD_TIMING_1_VFP_MASK 0x00FF0000 // Vertical Front Porch +#define LCD_TIMING_1_VSW_MASK 0x0000FC00 // Vertical Sync Pulse Width +#define LCD_TIMING_1_LPS_MASK 0x000003FF // Lines Per Screen + +/* +// LCD Timing 2 Register (TIMING_2) +*/ +#define LCD_TIMING_2_AC (1 << 31) // Invert Output Enable +#define LCD_TIMING_2_IPC (1 << 30) // Invert Pixel Clock +#define LCD_TIMING_2_IHS (1 << 29) // Invert Hsync +#define LCD_TIMING_2_IVS (1 << 28) // Invert Vsync +#define LCD_TIMING_2_BCD (1 << 27) // Bypass Pixel Clock Divider +#define LCD_TIMING_2_ACB_MASK 0x01F00000 // AC Bias Pin Frequency Mask +#define LCD_TIMING_2_CPL_MASK 0x0003FF00 // Clocks Per Line Mask +#define LCD_TIMING_2_LCS (1 << 7) // LCD Clock source selection +#define LCD_TIMING_2_LCD_MASK 0x00000060 // +#define LCD_TIMING_2_PCD_MASK 0x0000001F // Pixel Clock Divisor Mask + +/* +#define LCD_TIMING_2_BCD (1 << 26) // Bypass Pixel Clock Divider +#define LCD_TIMING_2_CPL_MASK 0x03FF0000 // Clocks Per Line Mask +#define LCD_TIMING_2_SLV (1 << 15) // Slave mode +#define LCD_TIMING_2_IEO (1 << 14) // Invert Output Enable +#define LCD_TIMING_2_IPC (1 << 13) // Invert Pixel Clock +#define LCD_TIMING_2_IHS (1 << 12) // Invert Hsync +#define LCD_TIMING_2_IVS (1 << 11) // Invert Vsync +#define LCD_TIMING_2_ACB_MASK 0x000007C0 // AC Bias Pin Frequency Mask +#define LCD_TIMING_2_LCS (1 << 5) // LCD Clock source selection +#define LCD_TIMING_2_PCD_MASK 0x0000001F // Pixel Clock Divisor Mask +*/ +/* +///////////////////////////////////////////////////////////////////////////////////////// +// ADC Interface Controller +*/ +#define ADC_ADCCR_OFFSET 0 +#define ADC_ADCTPCR_OFFSET 0x04 +#define ADC_ADCBACR_OFFSET 0x08 +#define ADC_ADCISR_OFFSET 0x10 +#define ADC_ADCTDCSR_OFFSET 0x1C +#define ADC_ADCDIRCR_OFFSET 0x20 +#define ADC_ADCDIRDATA_OFFSET 0x24 +#define ADC_ADCTPXDR0_OFFSET 0x30 +#define ADC_ADCTPXDR1_OFFSET 0x34 +#define ADC_ADCTPYDR0_OFFSET 0x38 +#define ADC_ADCTPYDR1_OFFSET 0x3C +#define ADC_ADCTPXDR2_OFFSET 0x40 +#define ADC_ADCTPXDR3_OFFSET 0x44 +#define ADC_ADCTPYDR2_OFFSET 0x48 +#define ADC_ADCTPYDR3_OFFSET 0x4C +#define ADC_ADCMBDATA_OFFSET 0x50 + +#define ADC_ADCCR (ADC_BASE + ADC_ADCCR_OFFSET) // ADC control register +#define ADC_ADCTPCR (ADC_BASE + ADC_ADCTPCR_OFFSET) // Touch panel control +#define ADC_ADCBACR (ADC_BASE + ADC_ADCBACR_OFFSET) // Battery check control +#define ADC_ADCISR (ADC_BASE + ADC_ADCISR_OFFSET) // ADC Interrupt Status +#define ADC_ADCTDCSR (ADC_BASE + ADC_ADCTDCSR_OFFSET) // Tipdown Control/Status +#define ADC_ADCDIRCR (ADC_BASE + ADC_ADCDIRCR_OFFSET) // ADC direct control +#define ADC_ADCDIRDATA (ADC_BASE + ADC_ADCDIRDATA_OFFSET) // ADC direct data read +#define ADC_ADCTPXDR0 (ADC_BASE + ADC_ADCTPXDR0_OFFSET) // Touch panel data [X1:X0] 1st Read +#define ADC_ADCTPXDR1 (ADC_BASE + ADC_ADCTPXDR1_OFFSET) // Touch panel data [X3:X2] 1st Read +#define ADC_ADCTPYDR0 (ADC_BASE + ADC_ADCTPYDR0_OFFSET) // Touch panel data [Y1:Y0] 1st Read +#define ADC_ADCTPYDR1 (ADC_BASE + ADC_ADCTPYDR1_OFFSET) // Touch panel data [Y3:Y2] 1st Read +#define ADC_ADCTPXDR2 (ADC_BASE + ADC_ADC_ADCTPXDR2_OFFSET) // Touch panel data [X1:X0] 2nd Read +#define ADC_ADCTPXDR3 (ADC_BASE + ADC_ADCTPXDR3_OFFSET) // Touch panel data [X3:X2] 2nd Read +#define ADC_ADCTPYDR2 (ADC_BASE + ADC_ADCTPYDR2_OFFSET) // Touch panel data [Y1:Y0] 2nd Read +#define ADC_ADCTPYDR3 (ADC_BASE + ADC_ADCTPYDR3_OFFSET) // Touch panel data [Y3:Y2] 2nd Read +#define ADC_ADCMBDATA (ADC_BASE + ADC_ADCMBDATA_OFFSET) // Main battery check data + +/* +// ADC Control Register +*/ +#define ADC_ADCCR_ADCPD (1 << 7) +#define ADC_ADCCR_DIRECTC (1 << 6) +#define ADC_ADCCR_WAIT_MASK 0x0C +#define ADC_ADCCR_SOP (1 << 1) +#define ADC_ADCCR_LONGCAL (1 << 0) + +/* +// ADC Touch Panel Control Register (ADCTPCR) +*/ +#define ADC_ADCTPCR_TPEN (1 << 7) +#define ADC_ADCTPCR_TINTMSK (1 << 6) +#define ADC_ADCTPCR_SWBYPSS (1 << 5) +#define ADC_ADCTPCR_SWINVT (1 << 4) +#define ADC_ADCTPCR_INTTDEN (1 << 3) +#define ADC_ADCTPCR_SSHOT (1 << 2) +#define ADC_ADCTPCR_TRATE_MASK 0x03 + +/* +// ADC Battery check Control Register (ADCBACR) +*/ +#define ADC_ADCBACR_BEN (1 << 1) +#define ADC_ADCBACR_INTMSK (1 << 0) + +/* +// ADC Interrupt Status Register (ADCISR) +*/ +#define ADC_ADCISR_INTTP (1 << 3) +#define ADC_ADCISR_INTTB (1 << 2) +#define ADC_ADCISR_INTTD (1 << 1) +#define ADC_ADCISR_INTTU (1 << 0) + +/* +// ADC Tip Down Control Status Register (ADCTDCSR) +*/ +#define ADC_ADCTDCSR_TDEN (1 << 7) +#define ADC_ADCTDCSR_TDMSK (1 << 6) +#define ADC_ADCTDCSR_TUEN (1 << 5) +#define ADC_ADCTDCSR_TUMSK (1 << 4) +#define ADC_ADCTDCSR_TPSEL (1 << 3) +#define ADC_ADCTDCSR_TP_X (1 << 1) +#define ADC_ADCTDCSR_TP_Y (1 << 0) + +/* +// ADC Direct Control Register (ADCDIRCR) +*/ +#define ADC_ADCDIRCR_AIOSTOP (1 << 7) +#define ADC_ADCDIRCR_ACH_MASK 0x1F +#define ADC_ADCDIRCR_ACH_CHANNEL_0 (1 << 0) // touch panel X +#define ADC_ADCDIRCR_ACH_CHANNEL_1 (1 << 1) // touch panel Y +#define ADC_ADCDIRCR_ACH_CHANNEL_2 (1 << 2) // Main battery +#define ADC_ADCDIRCR_ACH_CHANNEL_3 (1 << 3) // Backup battery + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// UART & SMART CARD Controller Register +*/ +#define UART0_OFFSET 0 +#define UART1_OFFSET 0x1000 +#define UART2_OFFSET 0x2000 +#define UART3_OFFSET 0x3000 +#define UART4_OFFSET 0x4000 +#define UART5_OFFSET 0x5000 + +#define UART0_BASE (UART_BASE + UART0_OFFSET) +#define UART1_BASE (UART_BASE + UART1_OFFSET) +#define UART2_BASE (UART_BASE + UART2_OFFSET) +#define UART3_BASE (UART_BASE + UART3_OFFSET) +#define UART4_BASE (UART_BASE + UART4_OFFSET) +#define UART5_BASE (UART_BASE + UART5_OFFSET) + +#define UART_RBR_OFFSET 0 +#define UART_THR_OFFSET 0 +#define UART_DLL_OFFSET 0 +#define UART_IER_OFFSET 0x04 +#define UART_DLM_OFFSET 0x04 +#define UART_IIR_OFFSET 0x08 +#define UART_FCR_OFFSET 0x08 +#define UART_LCR_OFFSET 0x0c +#define UART_SMR_OFFSET 0x10 +#define UART_MCR_OFFSET 0x10 +#define UART_LSR_OFFSET 0x14 +#define UART_SSR_OFFSET 0x18 +#define UART_MSR_OFFSET 0x18 +#define UART_SCR_OFFSET 0x1C +#define UART_RTR_OFFSET 0x20 +#define UART_RNR_OFFSET 0x24 +#define UART_WTR_OFFSET 0x28 +#define UART_EGR_OFFSET 0x2C +#define UART_UCR_OFFSET 0x30 + +#define UART0_RBR (UART0_BASE + UART_RBR_OFFSET) +#define UART0_THR (UART0_BASE + UART_THR_OFFSET) +#define UART0_DLL (UART0_BASE + UART_DLL_OFFSET) +#define UART0_IER (UART0_BASE + UART_IER_OFFSET) +#define UART0_DLM (UART0_BASE + UART_DLM_OFFSET) +#define UART0_IIR (UART0_BASE + UART_IIR_OFFSET) +#define UART0_FCR (UART0_BASE + UART_FCR_OFFSET) +#define UART0_LCR (UART0_BASE + UART_LCR_OFFSET) +#define UART0_SMR (UART0_BASE + UART_SMR_OFFSET) +#define UART0_MCR (UART0_BASE + UART_MCR_OFFSET) +#define UART0_LSR (UART0_BASE + UART_LSR_OFFSET) +#define UART0_SSR (UART0_BASE + UART_SSR_OFFSET) +#define UART0_MSR (UART0_BASE + UART_MSR_OFFSET) +#define UART0_SCR (UART0_BASE + UART_SCR_OFFSET) +#define UART0_RTR (UART0_BASE + UART_RTR_OFFSET) +#define UART0_RNR (UART0_BASE + UART_RNR_OFFSET) +#define UART0_WTR (UART0_BASE + UART_WTR_OFFSET) +#define UART0_EGR (UART0_BASE + UART_EGR_OFFSET) +#define UART0_UCR (UART0_BASE + UART_UCR_OFFSET) + +#define UART1_RBR (UART1_BASE + UART_RBR_OFFSET) +#define UART1_THR (UART1_BASE + UART_THR_OFFSET) +#define UART1_DLL (UART1_BASE + UART_DLL_OFFSET) +#define UART1_IER (UART1_BASE + UART_IER_OFFSET) +#define UART1_DLM (UART1_BASE + UART_DLM_OFFSET) +#define UART1_IIR (UART1_BASE + UART_IIR_OFFSET) +#define UART1_FCR (UART1_BASE + UART_FCR_OFFSET) +#define UART1_LCR (UART1_BASE + UART_LCR_OFFSET) +#define UART1_SMR (UART1_BASE + UART_SMR_OFFSET) +#define UART1_MCR (UART1_BASE + UART_MCR_OFFSET) +#define UART1_LSR (UART1_BASE + UART_LSR_OFFSET) +#define UART1_SSR (UART1_BASE + UART_SSR_OFFSET) +#define UART1_MSR (UART1_BASE + UART_MSR_OFFSET) +#define UART1_SCR (UART1_BASE + UART_SCR_OFFSET) +#define UART1_RTR (UART1_BASE + UART_RTR_OFFSET) +#define UART1_RNR (UART1_BASE + UART_RNR_OFFSET) +#define UART1_WTR (UART1_BASE + UART_WTR_OFFSET) +#define UART1_EGR (UART1_BASE + UART_EGR_OFFSET) +#define UART1_UCR (UART1_BASE + UART_UCR_OFFSET) + +#define UART2_RBR (UART2_BASE + UART_RBR_OFFSET) +#define UART2_THR (UART2_BASE + UART_THR_OFFSET) +#define UART2_DLL (UART2_BASE + UART_DLL_OFFSET) +#define UART2_IER (UART2_BASE + UART_IER_OFFSET) +#define UART2_DLM (UART2_BASE + UART_DLM_OFFSET) +#define UART2_IIR (UART2_BASE + UART_IIR_OFFSET) +#define UART2_FCR (UART2_BASE + UART_FCR_OFFSET) +#define UART2_LCR (UART2_BASE + UART_LCR_OFFSET) +#define UART2_MCR (UART2_BASE + UART_MCR_OFFSET) +#define UART2_LSR (UART2_BASE + UART_LSR_OFFSET) +#define UART2_MSR (UART2_BASE + UART_MSR_OFFSET) +#define UART2_SCR (UART2_BASE + UART_SCR_OFFSET) +#define UART2_UCR (UART2_BASE + UART_UCR_OFFSET) + +#define UART3_RBR (UART3_BASE + UART_RBR_OFFSET) +#define UART3_THR (UART3_BASE + UART_THR_OFFSET) +#define UART3_DLL (UART3_BASE + UART_DLL_OFFSET) +#define UART3_IER (UART3_BASE + UART_IER_OFFSET) +#define UART3_DLM (UART3_BASE + UART_DLM_OFFSET) +#define UART3_IIR (UART3_BASE + UART_IIR_OFFSET) +#define UART3_FCR (UART3_BASE + UART_FCR_OFFSET) +#define UART3_LCR (UART3_BASE + UART_LCR_OFFSET) +#define UART3_MCR (UART3_BASE + UART_MCR_OFFSET) +#define UART3_LSR (UART3_BASE + UART_LSR_OFFSET) +#define UART3_MSR (UART3_BASE + UART_MSR_OFFSET) +#define UART3_SCR (UART3_BASE + UART_SCR_OFFSET) +#define UART3_UCR (UART3_BASE + UART_UCR_OFFSET) + +#define UART4_RBR (UART4_BASE + UART_RBR_OFFSET) +#define UART4_THR (UART4_BASE + UART_THR_OFFSET) +#define UART4_DLL (UART4_BASE + UART_DLL_OFFSET) +#define UART4_IER (UART4_BASE + UART_IER_OFFSET) +#define UART4_DLM (UART4_BASE + UART_DLM_OFFSET) +#define UART4_IIR (UART4_BASE + UART_IIR_OFFSET) +#define UART4_FCR (UART4_BASE + UART_FCR_OFFSET) +#define UART4_LCR (UART4_BASE + UART_LCR_OFFSET) +#define UART4_MCR (UART4_BASE + UART_MCR_OFFSET) +#define UART4_LSR (UART4_BASE + UART_LSR_OFFSET) +#define UART4_MSR (UART4_BASE + UART_MSR_OFFSET) +#define UART4_SCR (UART4_BASE + UART_SCR_OFFSET) +#define UART4_UCR (UART4_BASE + UART_UCR_OFFSET) + +#define UART5_RBR (UART5_BASE + UART_RBR_OFFSET) +#define UART5_THR (UART5_BASE + UART_THR_OFFSET) +#define UART5_DLL (UART5_BASE + UART_DLL_OFFSET) +#define UART5_IER (UART5_BASE + UART_IER_OFFSET) +#define UART5_DLM (UART5_BASE + UART_DLM_OFFSET) +#define UART5_IIR (UART5_BASE + UART_IIR_OFFSET) +#define UART5_FCR (UART5_BASE + UART_FCR_OFFSET) +#define UART5_LCR (UART5_BASE + UART_LCR_OFFSET) +#define UART5_MCR (UART5_BASE + UART_MCR_OFFSET) +#define UART5_LSR (UART5_BASE + UART_LSR_OFFSET) +#define UART5_MSR (UART5_BASE + UART_MSR_OFFSET) +#define UART5_SCR (UART5_BASE + UART_SCR_OFFSET) +#define UART5_UCR (UART5_BASE + UART_UCR_OFFSET) + +/* +// Interrupt Enable Register (IER) UART +*/ +#define UART_IER_MS_INTR (1 << 3) +#define UART_IER_LS_INTR (1 << 2) +#define UART_IER_TX_EMPTY_INTR (1 << 1) +#define UART_IER_DATA_RDY_INTR (1 << 0) + +/* +// Interrupt Enable Register (IER) SMART CARD +*/ +#define SUART_IER_CARD_DET_INTR (1 << 5) +#define SUART_IER_WAIT_TIME_INTR (1 << 4) +#define SUART_IER_TX_LS_INTR (1 << 3) +#define SUART_IER_RX_LS_INTR (1 << 2) +#define SUART_IER_TX_EMPTY_INTR (1 << 1) +#define SUART_IER_DATA_RDY_INTR (1 << 0) + +/* +// Interrupt Identification Register (IIR) UART +*/ +#define UART_IIR_INTR_PEND (1 << 0) +#define UART_IIR_INTR_ID_MASK 0x0E // Interrupt ID Mask +#define UART_IIR_INTR_ID_MS (0 << 1) // Modem Status +#define UART_IIR_INTR_ID_THRE (1 << 1) // Transmitter Holding Register Empty +#define UART_IIR_INTR_ID_RDA (2 << 1) // Receiver Data Available +#define UART_IIR_INTR_ID_RLS (3 << 1) // Receiver Line Status +#define UART_IIR_INTR_ID_CTI (6 << 1) // Character Time-out Indication +#define UART_IIR_FIFO_EN_MASK 0xC0 + +/* +// Interrupt Identification Register (IIR) SMART CARD +*/ +#define SUART_IIR_INTR_PEND (1 << 0) +#define SUART_IIR_INTR_ID_MASK 0x1E // Interrupt ID Mask +#define SUART_IIR_INTR_ID_WT (0 << 1) // Waiting Timeout +#define SUART_IIR_INTR_ID_THRE (1 << 1) // Transmitter Holding Register Empty +#define SUART_IIR_INTR_ID_RDA (2 << 1) // Receiver Data Available +#define SUART_IIR_INTR_ID_RLS (3 << 1) // Receiver Line Status +#define SUART_IIR_INTR_ID_CDS (4 << 1) // Card Detect Status +#define SUART_IIR_INTR_ID_CIF (8 << 1) // Card Initialization Fail +#define SUART_IIR_INTR_ID_CTI (10 << 1) // Character Time-out Indication +#define SUART_IIR_INTR_ID_TLD (11 << 1) // Transmitter Line Status +#define SUART_IIR_FIFO_EN_MASK 0xC0 + +/* +// 16550 or 16550a device type check +#define UART_IIR_MS 0x00 +#define UART_IIR_NIP 0x01 +#define UART_IIR_TX 0x02 +#define UART_IIR_RX 0x04 +#define UART_IIR_LS 0x06 +#define UART_IIR_RXTO 0x0C +#define UART_IIR_64B_FIFO 0x20 +#define UART_IIR_FIFO_WORKS 0x40 +#define UART_IIR_FIFO_EN 0x80 +*/ + +/* +// FIFO Control Register (FCR) +*/ +#define UART_FCR_RCVR_TRIG_LEVEL_MASK 0xC0 // RDVR FIFO Trigger Level Mask +#define UART_FCR_RCVR_TRIG_LEVEL_1 0 // RDVR FIFO Trigger Level 01 +#define UART_FCR_RCVR_TRIG_LEVEL_4 (1 << 6) // RDVR FIFO Trigger Level 04 +#define UART_FCR_RCVR_TRIG_LEVEL_8 (2 << 6) // RDVR FIFO Trigger Level 08 +#define UART_FCR_RCVR_TRIG_LEVEL_14 (3 << 6) // RDVR FIFO Trigger Level 14 +#define UART_FCR_XMIT_RESET (1 << 2) // clear XMIT Fifo +#define UART_FCR_RCVR_RESET (1 << 1) // clear RCVR Fifo +#define UART_FCR_FIFO_EN (1 << 0) // Enable FIFO + +/* +// Line Control Register (LCR) +*/ +#define UART_LCR_DLAB (1 << 7) // Divisor Latch Access bit +#define UART_LCR_SET_BREAK (1 << 6) // Set Break Control +#define UART_LCR_STICK_PARITY (1 << 5) // Stick Parity +#define UART_LCR_EVEN_PARITY_SET (1 << 4) // Even Parity Select +#define UART_LCR_PARITY_ENABLE (1 << 3) // Parity Enable +#define UART_LCR_NO_PARITY 0 +#define UART_LCR_EVEN_PARITY (UART_LCR_EVEN_PARITY_SET | UART_LCR_PARITY_ENABLE) +#define UART_LCR_ODD_PARITY (UART_LCR_PARITY_ENABLE) +#define UART_LCR_MARK_PARITY (UART_LCR_STICK_PARITY | UART_LCR_PARITY_ENABLE) +#define UART_LCR_SPACE_PARITY (UART_LCR_STICK_PARITY | UART_LCR_EVEN_PARITY_SET | UART_LCR_PARITY_ENABLE) +#define UART_LCR_STOPBIT_NUMBER (1 << 2) // Stop bits. b0: 1 stop bit, b1: 2 stop bit +#define UART_LCR_WORD_SELECT (1 << 1) +#define UART_LCR_LENGTH (1 << 0) + +#define UART_LCR_CHAR_LEN_5 0 // 5 bits Character Length +#define UART_LCR_CHAR_LEN_6 0x01 // 6 bits Character Length +#define UART_LCR_CHAR_LEN_7 0x02 // 7 bits Character Length +#define UART_LCR_CHAR_LEN_8 0x03 // 8 bits Character Length + +/* +// Modem Control Register (MCR) UART +*/ +#define UART_MCR_LOOP (1 << 4) +#define UART_MCR_RTS (1 << 1) +#define UART_MCR_DTR (1 << 0) + +/* +// Smart Card Mode Register (SMR) SMART +*/ +#define SUART_SMR_DISINIT (1 << 11) +#define SUART_SMR_DIRCTLEN (1 << 10) +#define SUART_SMR_RSTVAL (1 << 9) +#define SUART_SMR_IOVAL (1 << 8) +#define SUART_SMR_CARDINIT (1 << 7) +#define SUART_SMR_RETRANEN (1 << 6) +#define SUART_SMR_DATAPOL (1 << 5) +#define SUART_SMR_DATADIR (1 << 3) +#define SUART_SMR_CLKVAL (1 << 2) +#define SUART_SMR_CLKEN (1 << 1) +#define SUART_SMR_BAUDSEL (1 << 0) + +/* +// Line Status Register (LSR) UART +*/ +#define UART_LSR_FIFO_ERR (1 << 7) // Fifo error +#define UART_LSR_TEMT (1 << 6) // Transmitter Empty +#define UART_LSR_THRE (1 << 5) // Transmitter Holding Register Empty +#define UART_LSR_BI (1 << 4) // Break Interrupt (BI) +#define UART_LSR_FE (1 << 3) // Framing Error (FE) +#define UART_LSR_PE (1 << 2) // Parity Error (PE) +#define UART_LSR_OE (1 << 1) // Overrun Error (OE) +#define UART_LSR_DR (1 << 0) // Data Ready (DR) + +/* +// Line Status Register (LSR) SMART +*/ +#define SUART_LSR_FIFO_ERR (1 << 7) // Fifo error +#define SUART_LSR_TEMT (1 << 6) // Transmitter Empty +#define SUART_LSR_THRE (1 << 5) // Transmitter Holding Register Empty +#define SUART_LSR_TXPE (1 << 4) // Transmitter Parity Error (THRE) +#define SUART_LSR_PE (1 << 2) // Parity Error (PE) +#define SUART_LSR_OE (1 << 1) // Overrun Error (OE) +#define SUART_LSR_DR (1 << 0) // Data Ready (DR) + +/* +// Modem Status Register (MSR) +*/ +#define UART_MSR_DCD (1 << 7) +#define UART_MSR_RI (1 << 6) +#define UART_MSR_DSR (1 << 5) +#define UART_MSR_CTS (1 << 4) +#define UART_MSR_DDCD (1 << 3) +#define UART_MSR_TERI (1 << 2) +#define UART_MSR_DDSR (1 << 1) +#define UART_MSR_DCTS (1 << 0) + +/* +// Smart Card Status Register (SSR) +*/ +#define SUART_SSR_RETRANS_TO (1 << 3) +#define SUART_SSR_WAITTIMEOUT (1 << 2) +#define SUART_SSR_INITFAIL (1 << 1) +#define SUART_SSR_CARDPRE (1 << 0) + +/* +// Uart Configuration Register (UCR) +*/ +#define UART_UCR_SMCARDEN (1 << 5) +#define UART_UCR_CLOCKSEL (1 << 4) +#define UART_UCR_SIR_LOOP_BACK (1 << 3) +#define UART_UCR_SIR_DUP (1 << 2) +#define UART_UCR_SIREN (1 << 1) +#define UART_UCR_UARTEN (1 << 0) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// SPI Controller Register +*/ +#define SPI0_OFFSET 0 +#define SPI1_OFFSET 0x1000 + +#define SPI0_BASE (SPI_BASE + SPI0_OFFSET) +#define SPI1_BASE (SPI_BASE + SPI1_OFFSET) + +#define SPI_SSPCR0_OFFSET 0 +#define SPI_SSPCR1_OFFSET 0x04 +#define SPI_SSPDR_OFFSET 0x08 +#define SPI_SSPSR_OFFSET 0x0C +#define SPI_SSPCSR_OFFSET 0x10 +#define SPI_SSPIIR_OFFSET 0x14 +#define SPI_SSPICR_OFFSET 0x14 +#define SPI_SSPFENT_OFFSET 0x18 +#define SPI_SSPIENT_OFFSET 0x1C +#define SPI_SSPTCER_OFFSET 0x40 + +#define SPI0_SSPCR0 (SPI0_BASE + SPI_SSPCR0_OFFSET) +#define SPI0_SSPCR1 (SPI0_BASE + SPI_SSPCR1_OFFSET) +#define SPI0_SSPDR (SPI0_BASE + SPI_SSPDR_OFFSET) +#define SPI0_SSPSR (SPI0_BASE + SPI_SSPSR_OFFSET) +#define SPI0_SSPCSR (SPI0_BASE + SPI_SSPCSR_OFFSET) +#define SPI0_SSPIIR (SPI0_BASE + SPI_SSPIIR_OFFSET) +#define SPI0_SSPICR (SPI0_BASE + SPI_SSPICR_OFFSET) +#define SPI0_SSPFENT (SPI0_BASE + SPI_SSPFENT_OFFSET) +#define SPI0_SSPIENT (SPI0_BASE + SPI_SSPIENT_OFFSET) +#define SPI0_SSPTCER (SPI0_BASE + SPI_SSPTCER_OFFSET) + +#define SPI1_SSPCR0 (SPI1_BASE + SPI_SSPCR0_OFFSET) +#define SPI1_SSPCR1 (SPI1_BASE + SPI_SSPCR1_OFFSET) +#define SPI1_SSPDR (SPI1_BASE + SPI_SSPDR_OFFSET) +#define SPI1_SSPSR (SPI1_BASE + SPI_SSPSR_OFFSET) +#define SPI1_SSPCSR (SPI1_BASE + SPI_SSPCSR_OFFSET) +#define SPI1_SSPIIR (SPI1_BASE + SPI_SSPIIR_OFFSET) +#define SPI1_SSPICR (SPI1_BASE + SPI_SSPICR_OFFSET) +#define SPI1_SSPFENT (SPI1_BASE + SPI_SSPFENT_OFFSET) +#define SPI1_SSPIENT (SPI1_BASE + SPI_SSPIENT_OFFSET) +#define SPI1_SSPTCER (SPI1_BASE + SPI_SSPTCER_OFFSET) + +/* +// SPI Control Register 0 (SSPCR0) +*/ +#define SPI_SSPCR0_GSEL (1 << 4) +#define SPI_SSPCR0_SDIR (1 << 3) +#define SPI_SSPCR0_SPH (1 << 2) +#define SPI_SSPCR0_SPO (1 << 1) +#define SPI_SSPCR0_MS (1 << 0) + +/* +// SPI Control Register 1 (SSPCR1) +*/ +#define SPI_SSPCR1_SSE (1 << 3) +#define SPI_SSPCR1_RORIE (1 << 2) +#define SPI_SSPCR1_TIE (1 << 1) +#define SPI_SSPCR1_RIE (1 << 0) + +/* +// SPI Status Register (SSPSR) +*/ +#define SPI_SSPSR_BSY (1 << 4) +#define SPI_SSPSR_RFF (1 << 3) +#define SPI_SSPSR_RNE (1 << 2) +#define SPI_SSPSR_TNF (1 << 1) +#define SPI_SSPSR_TFE (1 << 0) + +/* +// SPI Interrupt Status/Clear Register (SSPIIR/SSPICR) +*/ +#define SPI_SSPIIR_RORIS (1 << 2) +#define SPI_SSPIIR_TIS (1 << 1) +#define SPI_SSPIIR_RIS (1 << 0) + +#define SPI_SSPICR_RORIS (1 << 2) +#define SPI_SSPICR_TIS (1 << 1) +#define SPI_SSPICR_RISE (1 << 0) + + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// SMC Controller Register +*/ +#define SMC_SMCCMD_OFFSET 0 +#define SMC_SMCADR_OFFSET 0x04 +#define SMC_SMC_SMCDATW_OFFSET 0x08 +#define SMC_SMCDATR_OFFSET 0x0C +#define SMC_SMCCONF_OFFSET 0x10 +#define SMC_SMCTIME_OFFSET 0x14 +#define SMC_SMCSTAT_OFFSET 0x1C +#define SMC_SMCECC1_OFFSET 0x24 +#define SMC_SMCECC2_OFFSET 0x28 +#define SMC_SMCMRW_OFFSET 0x2C +#define SMC_SMCMSTAT_OFFSET 0x30 +#define SMC_SMCEBICONF_OFFSET 0x34 + +#define SMC_SMCCMD (SMC_BASE + SMC_SMCCMD_OFFSET) // SmartMedia Card Command register +#define SMC_SMCADR (SMC_BASE + SMC_SMCADR_OFFSET) // SmartMedia Card Address register +#define SMC_SMCDATW (SMC_BASE + SMC_SMCDATW_OFFSET) // Data written to SmartMedia Card +#define SMC_SMCDATR (SMC_BASE + SMC_SMCDATR_OFFSET) // Data received from SmartMedia Card +#define SMC_SMCCONF (SMC_BASE + SMC_SMCCONF_OFFSET) // SmartMedia Card controller configuration register +#define SMC_SMCTIME (SMC_BASE + SMC_SMCTIME_OFFSET) // Timing parameter register +#define SMC_SMCSTAT (SMC_BASE + SMC_SMCSTAT_OFFSET) // SmartMedia Card controller status register +#define SMC_SMCECC1 (SMC_BASE + SMC_SMCECC1_OFFSET) // ECC register for first half page data +#define SMC_SMCECC2 (SMC_BASE + SMC_SMCECC2_OFFSET) // ECC register for second half page data +#define SMC_SMCMRW (SMC_BASE + SMC_SMCMRW_OFFSET) // Multi-page read/write configuration register +#define SMC_SMCMSTAT (SMC_BASE + SMC_SMCMSTAT_OFFSET) // Multi-page read/write status register +#define SMC_SMCEBICONF (SMC_BASE + SMC_SMCEBICONF_OFFSET) // SMC for EBI Setting + +/* +// SMC Command Register (SMCCMD) +*/ +#define SMC_SMCCMD_HIDDEN_COMMAND_0_MASK 0xFF000000 +#define SMC_SMCCMD_HIDDEN_COMMAND_1_MASK 0x00FF0000 +#define SMC_SMCCMD_MAIN_COMMAND_MASK 0x0000FF00 +#define SMC_SMCCMD_SECOND_COMMAND_MASK 0x000000FF + +#define SMC_SMCCMD_MAIN_COMMAND_SERIAL_DATA_INPUT 0x80 +#define SMC_SMCCMD_MAIN_COMMAND_READ_0 0x00 +#define SMC_SMCCMD_MAIN_COMMAND_READ_1 0x01 +#define SMC_SMCCMD_MAIN_COMMAND_READ_2 0x50 +#define SMC_SMCCMD_MAIN_COMMAND_RESET 0xFF +#define SMC_SMCCMD_MAIN_COMMAND_PAGE_PROGRAM 0x10 +#define SMC_SMCCMD_MAIN_COMMAND_BLOCK_ERASE_1 0x60 +#define SMC_SMCCMD_MAIN_COMMAND_BLOCK_ERASE_2 0xD0 // ? +#define SMC_SMCCMD_MAIN_COMMAND_STATUS_READ 0x70 +#define SMC_SMCCMD_MAIN_COMMAND_ID_READ 0x90 + +/* +// SMC Address Register (SMCADR) +*/ +#define SMC_SMCADR_4MB_MASK 0x003FFFFF +#define SMC_SMCADR_8MB_MASK 0x007FFFFF +#define SMC_SMCADR_16MB_MASK 0x00FFFFFF +#define SMC_SMCADR_32MB_MASK 0x01FFFFFF +#define SMC_SMCADR_64MB_MASK 0x03FFFFFF +#define SMC_SMCADR_128MB_MASK 0x7FFFFFFF + +/* +// SMC Data Write Register (SMCDATW) +*/ +#define SMC_SMCDATW_3_BYTE_DATA_MASK 0xFF000000 +#define SMC_SMCDATW_2_BYTE_DATA_MASK 0x00FF0000 +#define SMC_SMCDATW_1_BYTE_DATA_MASK 0x0000FF00 +#define SMC_SMCDATW_0_BYTE_DATA_MASK 0x000000FF + +/* +// SMC Data Read Register (SMCDATR) +*/ +#define SMC_SMCDATR_3_BYTE_DATA_MASK 0xFF000000 +#define SMC_SMCDATR_2_BYTE_DATA_MASK 0x00FF0000 +#define SMC_SMCDATR_1_BYTE_DATA_MASK 0x0000FF00 +#define SMC_SMCDATR_0_BYTE_DATA_MASK 0x000000FF + +/* +// SMC Configuration Register (SMCCONF) +*/ +#define SMC_SMCCONF_POWER_ENABLE 0x80000000 //(1 << 31) +#define SMC_SMCCONF_MULTI_PAGE_WRITE_ENABLE (1 << 10) +#define SMC_SMCCONF_MULTI_PAGE_READ_ENABLE (1 << 9) +#define SMC_SMCCONF_WRITE_ECC_ENABLE (1 << 8) +#define SMC_SMCCONF_READ_ECC_ENABLE (1 << 7) +#define SMC_SMCCONF_SAFE_MARGIN (1 << 6) +#define SMC_SMCCONF_SMC_ENABLE (1 << 5) +#define SMC_SMCCONF_INTR_EN (1 << 3) +#define SMC_SMCCONF_UNIQUE_ID_EN (1 << 1) +#define SMC_SMCCONF_BIG_CARD_ENABLE (1 << 0) + +/* +// SMC Timing Parameter Register (SMCTIME) +*/ +#define SMC_SMCTIME_WAIT_COUNTER_MASK 0x0F000000 +#define SMC_SMCTIME_BYTE_COUNTER_MASK 0x007F0000 +#define SMC_SMCTIME_HIGH_COUNTER_MASK 0x00000300 +#define SMC_SMCTIME_LOW_COUNTER_MASK 0x00000007 + +/* +// SMC Status Register (SMCSTAT) +*/ +#define SMC_SMCSTAT_CD_INTR (1 << 31) +#define SMC_SMCSTAT_NSMCE (1 << 30) +#define SMC_SMCSTAT_SMCLE (1 << 29) +#define SMC_SMCSTAT_SMALE (1 << 28) +#define SMC_SMCSTAT_NSMWE (1 << 27) +#define SMC_SMCSTAT_NSMRE (1 << 26) +#define SMC_SMCSTAT_NSMWP (1 << 25) +#define SMC_SMCSTAT_SMR_B (1 << 24) +#define SMC_SMCSTAT_CURRENT_COMMAND_CARD_DETECT_NOTIFICATION_MASK 0x00FF0000 +#define SMC_SMCSTAT_EXTRA_AREA (1 << 15) +#define SMC_SMCSTAT_BYTE_COUNT_MASK 0x00007F00 +#define SMC_SMCSTAT_INTERNAL_STATE_MASK 0x000000F0 +#define SMC_SMCSTAT_CARD_DETECT (1 << 3) +#define SMC_SMCSTAT_IRQ (1 << 2) +#define SMC_SMCSTAT_BUSY (1 << 0) + +/* +// SMC Multi-page Read/Write Configuration Register (SMCMRW) +*/ +#define SMC_SMCMRW_PAGE_SIZE_FOR_READ_MASK 0x0000003F +#define SMC_SMCMRW_PAGE_SIZE_FOR_WRITE_MASK 0x00000FC0 + +/* +// SMC Multi-page Read/Write Status Register (SMCSTAT) +*/ +#define SMC_SMCMRW_READ_PAGE_COUNT_MASK 0x0000003F +#define SMC_SMCMRW_WRITE_PAGE_COUNT_MASK 0x00000FC0 + +/* +// SMC for EBI Setting +*/ +#define SMC_SMCEBICONF_EBI_SELECT (1 << 2) +#define SMC_SMCEBICONF_WP (1 << 1) +#define SMC_SMCEBICONF_CE (1 << 0) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// I2C Controller Register +*/ +#define I2C_DATAREG_OFFSET 0 +#define I2C_TARGETREG_OFFSET 0x04 +#define I2C_STATUSREG_OFFSET 0x08 +#define I2C_SLAVEREG_OFFSET 0x0C +#define I2C_INTMASKREG_OFFSET 0x10 +#define I2C_CONFIGREG_OFFSET 0x14 +#define I2C_BAUDREG_OFFSET 0x18 +#define I2C_FIFOCONREG_OFFSET 0x1C +#define I2C_RXBUFFER_OFFSET 0x20 + +#define I2C_DATAREG (I2C_BASE + I2C_DATAREG_OFFSET) +#define I2C_TARGETREG (I2C_BASE + I2C_TARGETREG_OFFSET) +#define I2C_STATUSREG (I2C_BASE + I2C_STATUSREG_OFFSET) +#define I2C_SLAVEREG (I2C_BASE + I2C_SLAVEREG_OFFSET) +#define I2C_INTMASKREG (I2C_BASE + I2C_INTMASKREG_OFFSET) +#define I2C_CONFIGREG (I2C_BASE + I2C_CONFIGREG_OFFSET) +#define I2C_BAUDREG (I2C_BASE + I2C_BAUDREG_OFFSET) +#define I2C_FIFOCONREG (I2C_BASE + I2C_FIFOCONREG_OFFSET) +#define I2C_RXBUFFER (I2C_BASE + I2C_RXBUFFER_OFFSET) + +/* +// Target Register (TARGETREG) +*/ +#define I2C_TARGETREG_ADDR_MASK 0XFE +#define I2C_TARGETREG_ADDR_READ (1 << 0) +#define I2C_TARGETREG_ADDR_WRITE (0 << 0) + +/* +// Status Register (STATUSREG) +*/ +#define I2C_STATUSREG_FIFOOVF (1 << 15) +#define I2C_STATUSREG_FIFOFULL (1 << 14) +#define I2C_STATUSREG_FIFOUF (1 << 13) +#define I2C_STATUSREG_FIFOEMPTY (1 << 12) +#define I2C_STATUSREG_XDREQ (1 << 11) +#define I2C_STATUSREG_TRANSMITTER (1 << 8) +#define I2C_STATUSREG_TRANSREQ (1 << 7) +#define I2C_STATUSREG_STOPREQ (1 << 6) +#define I2C_STATUSREG_EOTREQ (1 << 5) +#define I2C_STATUSREG_DATAREQ (1 << 4) +#define I2C_STATUSREG_BUSLOST (1 << 3) +#define I2C_STATUSREG_BUSBUSY (1 << 2) +#define I2C_STATUSREG_ACK_RCV (1 << 1) +#define I2C_STATUSREG_MASTER (1 << 0) + +/* +// Interrupt Mask Register (INTMASKREG) +*/ +#define I2C_INTMASKREG_FIFOEMPTY (1 << 7) //s.y.s +#define I2C_INTMASKREG_FIFOFULL (1 << 6) //s.y.s +#define I2C_INTMASKREG_XDREQ (1 << 5) // s.y.s +#define I2C_INTMASKREG_TRANSREQ (1 << 4) // s.y.s +#define I2C_INTMASKREG_STOPREQ (1 << 3) //s.y.s +#define I2C_INTMASKREG_EOTREQ (1 << 2) // s.y.s +#define I2C_INTMASKREG_DATAREGREQ (1 << 1) //s.y.s +#define I2C_INTMASKREG_BUSLOSTM (1 << 0) + +/* +// Configuration Register (CONFIGREG) +*/ +#define I2C_CONFIGREG_RESTART (1 << 7) +#define I2C_CONFIGREG_SOFTRESET (1 << 5) +#define I2C_CONFIGREG_SINGLEBYTE (1 << 4) +#define I2C_CONFIGREG_TRANS_END (1 << 3) +#define I2C_CONFIGREG_SINGLEMODE (1 << 2) +#define I2C_CONFIGREG_FORCESTOP (1 << 1) +#define I2C_CONFIGREG_MASTER (1 << 0) + +/* +// FIFO Control Register (FIFOCONR) +*/ +#define I2C_FIFOCONR_TXFIFOEN (1 << 7) +#define I2C_FIFOCONR_RXFIFOEN (1 << 6) +#define I2C_FIFOCONR_RESET (1 << 5) +#define I2C_FIFOCONR_CLRDREQ (1 << 4) +#define I2C_FIFOCONR_FDD_MASK 0x0F + + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// Watchdog Timer Register +*/ +#define WDT_WDTCTRL_OFFSET 0 +#define WDT_WDTSTAT_OFFSET 0x04 +#define WDT_WDTCNT_OFFSET 0x08 + +#define WDT_WDTCTRL (WDT_BASE + WDT_WDTCTRL_OFFSET) +#define WDT_WDTSTAT (WDT_BASE + WDT_WDTSTAT_OFFSET) +#define WDT_WDTCNT (WDT_BASE + WDT_WDTCNT_OFFSET) + +/* +// Target Register (WDTCTRL) +*/ +#define WDT_WDTCTRL_INTREN (1 << 7) +#define WDT_WDTCTRL_MODESEL (1 << 6) +#define WDT_WDTCTRL_TMEN (1 << 5) +#define WDT_WDTCTRL_RSTEN (1 << 4) +#define WDT_WDTCTRL_RSTSEL (1 << 3) +#define WDT_WDTCTRL_CLK_SOURCE_SEL_MAKS 0x07 + +/* +// WDT Status Register (WDTSTAT) +*/ +#define WDT_WDTSTAT_ITOVF (1 << 1) +#define WDT_WDTSTAT_WTOVF (1 << 0) + + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// RTC Controller Register +*/ +#define RTC_RTCTRL_OFFSET 0 +#define RTC_RTCSTAT_OFFSET 0x04 +#define RTC_RTCSEC_OFFSET 0x08 +#define RTC_RTCMIN_OFFSET 0x0C +#define RTC_RTCHOR_OFFSET 0x10 +#define RTC_RTCDAY_OFFSET 0x14 +#define RTC_RTCMON_OFFSET 0x18 +#define RTC_RTCYER_OFFSET 0x1C +#define RTC_RTCWEK_OFFSET 0x20 +#define RTC_ALCTRL_OFFSET 0x24 +#define RTC_ALSEC_OFFSET 0x28 +#define RTC_ALMIN_OFFSET 0x2C +#define RTC_ALHOR_OFFSET 0x30 +#define RTC_ALDAY_OFFSET 0x34 +#define RTC_ALMON_OFFSET 0x38 +#define RTC_ALYER_OFFSET 0x3C +#define RTC_ALWEK_OFFSET 0x40 +#define RTC_TICTRL_OFFSET 0x44 +#define RTC_TICNT_OFFSET 0x48 +#define RTC_TIBASE_OFFSET 0x4C +#define RTC_PROTCTRL_OFFSET 0x60 +#define RTC_PROTECT1_OFFSET 0x7C +#define RTC_PROTECT2_OFFSET 0x64 +#define RTC_PROTECT3_OFFSET 0x78 +#define RTC_PROTECTLAST_OFFSET 0x6C +#define RTC_RTCTRLRESET_OFFSET 0x68 + +#define RTC_RTCTRL (RTC_BASE + RTC_RTCTRL_OFFSET) +#define RTC_RTCSTAT (RTC_BASE + RTC_RTCSTAT_OFFSET) +#define RTC_RTCSEC (RTC_BASE + RTC_RTCSEC_OFFSET) +#define RTC_RTCMIN (RTC_BASE + RTC_RTCMIN_OFFSET) +#define RTC_RTCHOR (RTC_BASE + RTC_RTCHOR_OFFSET) +#define RTC_RTCDAY (RTC_BASE + RTC_RTCDAY_OFFSET) +#define RTC_RTCMON (RTC_BASE + RTC_RTCMON_OFFSET) +#define RTC_RTCYER (RTC_BASE + RTC_RTCYER_OFFSET) +#define RTC_RTCWEK (RTC_BASE + RTC_RTCWEK_OFFSET) +#define RTC_ALCTRL (RTC_BASE + RTC_ALCTRL_OFFSET) +#define RTC_ALSEC (RTC_BASE + RTC_ALSEC_OFFSET) +#define RTC_ALMIN (RTC_BASE + RTC_ALMIN_OFFSET) +#define RTC_ALHOR (RTC_BASE + RTC_ALHOR_OFFSET) +#define RTC_ALDAY (RTC_BASE + RTC_ALDAY_OFFSET) +#define RTC_ALMON (RTC_BASE + RTC_ALMON_OFFSET) +#define RTC_ALYER (RTC_BASE + RTC_ALYER_OFFSET) +#define RTC_ALWEK (RTC_BASE + RTC_ALWEK_OFFSET) +#define RTC_TICTRL (RTC_BASE + RTC_TICTRL_OFFSET) +#define RTC_TICNT (RTC_BASE + RTC_TICNT_OFFSET) +#define RTC_TIBASE (RTC_BASE + RTC_TIBASE_OFFSET) +#define RTC_PROTCTRL (RTC_BASE + RTC_PROTCTRL_OFFSET) +#define RTC_PROTECT1 (RTC_BASE + RTC_PROTECT1_OFFSET) +#define RTC_PROTECT2 (RTC_BASE + RTC_PROTECT2_OFFSET) +#define RTC_PROTECT3 (RTC_BASE + RTC_PROTECT3_OFFSET) +#define RTC_PROTECTLAST (RTC_BASE + RTC_PROTECTLAST_OFFSET) +#define RTC_RTCTRLRESET (RTC_BASE + RTC_RTCTRLRESET_OFFSET) + +/* +// RTC Control Register (RTCTRL) +*/ +#define RTC_RTCTRL_EVTEN (1 << 5) +#define RTC_RTCTRL_INTEN (1 << 4) +#define RTC_RTCTRL_BATEN (1 << 3) +#define RTC_RTCTRL_CLK_SEL (1 << 2) +#define RTC_RTCTRL_RESET (1 << 1) +#define RTC_RTCTRL_RTCEN (1 << 0) + +/* +// RTC Status Register (RTCSTAT) +*/ +#define RTC_RTCSTAT_TICK_FLAG (1 << 2) +#define RTC_RTCSTAT_READ_FLAG (1 << 1) +#define RTC_RTCSTAT_ALM_FLAG (1 << 0) + +/* +// RTC Day of Week Register (RTCWEK) +*/ +#define RTC_RTCWEK_MASK 0x07 +#define RTC_RTCWEK_SAT 0 +#define RTC_RTCWEK_SUN 1 +#define RTC_RTCWEK_MON 2 +#define RTC_RTCWEK_TUE 3 +#define RTC_RTCWEK_WED 4 +#define RTC_RTCWEK_THU 5 +#define RTC_RTCWEK_FRI 6 + +/* +// RTC Alarm Control Register (ALCTRL) +*/ +#define RTC_ALCTRL_ALEN (1 << 7) +#define RTC_ALCTRL_ALWEKEN (1 << 6) +#define RTC_ALCTRL_ALYEREN (1 << 5) +#define RTC_ALCTRL_ALMONEN (1 << 4) +#define RTC_ALCTRL_ALDAYEN (1 << 3) +#define RTC_ALCTRL_ALHOREN (1 << 2) +#define RTC_ALCTRL_ALMINEN (1 << 1) +#define RTC_ALCTRL_ALSECEN (1 << 0) + +/* +// RTC Alarm Day of Week Register (RTCWEK) +*/ +#define RTC_ALWEK_MASK RTC_RTCWEK_MASK +#define RTC_ALWEK_SAT RTC_RTCWEK_SAT +#define RTC_ALWEK_SUN RTC_RTCWEK_SUN +#define RTC_ALWEK_MON RTC_RTCWEK_MON +#define RTC_ALWEK_TUE RTC_RTCWEK_TUE +#define RTC_ALWEK_WED RTC_RTCWEK_WED +#define RTC_ALWEK_THU RTC_RTCWEK_THU +#define RTC_ALWEK_FRI RTC_RTCWEK_FRI + +/* +// RTC Tick Timer Control Register (TICTRL) +*/ +#define RTC_TICTRL_TINTEN (1 << 6) + +#define RTC_TICTRL_CLKSEL_MASK 0x30 +#define RTC_TICTRL_CLKSEL_2048 (0 << 4) +#define RTC_TICTRL_CLKSEL_1024 (1 << 4) +#define RTC_TICTRL_CLKSEL_512 (2 << 4) +#define RTC_TICTRL_CLKSEL_128 (3 << 4) + +#define RTC_TICTRL_NPWDN (1 << 3) +#define RTC_TICTRL_CNTRESET_ON (1 << 2) + +#define RTC_TICTRL_CNTREPEAT_ON (1 << 1) +#define RTC_TICTRL_CNTREPEAT_OFF (0 << 1) + +#define RTC_TICTRL_CNTEN_ON (1 << 0) +#define RTC_TICTRL_CNTEN_OFF (0 << 0) + +/* +// RTC Reset Register (RTC_RTCTRLRESET) +*/ +#define RTC_RTCTRLRESET_CTRLRESET (1 << 0) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// KBD Controller Register +*/ +#define KBD_KBCR_OFFSET 0 +#define KBD_KBSC_OFFSET 0x04 +#define KBD_KBTR_OFFSET 0x08 +#define KBD_KBVR0_OFFSET 0x0C +#define KBD_KBVR1_OFFSET 0x10 +#define KBD_KBSR_OFFSET 0x18 + +#define KBD_KBCR (KBD_BASE + KBD_KBCR_OFFSET) +#define KBD_KBSC (KBD_BASE + KBD_KBSC_OFFSET) +#define KBD_KBTR (KBD_BASE + KBD_KBTR_OFFSET) +#define KBD_KBVR0 (KBD_BASE + KBD_KBVR0_OFFSET) +#define KBD_KBVR1 (KBD_BASE + KBD_KBVR1_OFFSET) +#define KBD_KBSR (KBD_BASE + KBD_KBSR_OFFSET) + +/* +// Keyboard Configuration Register (KBCR) +*/ +#define KBD_KBCR_SCAN_ENABLE (1 << 7) + +#define KBD_KBCR_NPOWER_DOWN_OFF (1 << 2) +#define KBD_KBCR_NPOWER_DOWN_ON (0 << 2) + +#define KBD_KBCR_CLK_SEL_MASK 0x03 +#define KBD_KBCR_CLK_SEL_PCLK_DIV_2 (0 << 0) /* // 00 = 1.84MHz */ +#define KBD_KBCR_CLK_SEL_PCLK_DIV_128 (1 << 0) /* // 01 = 28kHz */ +#define KBD_KBCR_CLK_SEL_PCLK_DIV_256 (2 << 0) /* // 10 = 14kHz */ +#define KBD_KBCR_CLK_SEL_PCLK_DIV_512 (3 << 0) /* // 11 = 7kHz */ + +/* +// Keyboard Scanout Register (KBSC) +*/ +/* +// Keyboard Value Register (KVR0) +*/ +#define KBD_KBVR0_1ST_COL_KSCANI 0xFF000000 +#define KBD_KBVR0_2ND_COL_KSCANI 0x00FF0000 +#define KBD_KBVR0_3RD_COL_KSCANI 0x0000FF00 +#define KBD_KBVR0_4TH_COL_KSCANI 0x000000FF + +/* +// Keyboard Value Register (KVR0) +*/ +#define KBD_KBVR0_5TH_COL_KSCANI 0xFF000000 +#define KBD_KBVR0_6TH_COL_KSCANI 0x00FF0000 + +/* +// Keyboard Value Register (KBSR) +*/ +#define KBD_KBSR_WAKEUP_EN (0 << 1) +#define KBD_KBSR_WAKEUP_DIS (1 << 1) + +#define KBD_KBSR_INTR_NOFULL (0 << 0) +#define KBD_KBSR_INTR_FULL (1 << 0) + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// GPIO Controller Register +*/ +#define ADATA_OFFSET 0 +#define ADIR_OFFSET 0x04 +#define AMASK_OFFSET 0x08 +#define ASTAT_OFFSET 0x0C +#define AEDGE_OFFSET 0x10 +#define ACLR_OFFSET 0x14 +#define APOL_OFFSET 0x18 +#define AEN_OFFSET 0x1C + +#define BDATA_OFFSET 0x20 +#define BDIR_OFFSET 0x24 +#define BMASK_OFFSET 0x28 +#define BSTAT_OFFSET 0x2C +#define BEDGE_OFFSET 0x30 +#define BCLR_OFFSET 0x34 +#define BPOL_OFFSET 0x38 +#define BEN_OFFSET 0x3C + +#define CDATA_OFFSET 0x40 +#define CDIR_OFFSET 0x44 +#define CMASK_OFFSET 0x48 +#define CSTAT_OFFSET 0x4C +#define CEDGE_OFFSET 0x50 +#define CCLR_OFFSET 0x54 +#define CPOL_OFFSET 0x58 +#define CEN_OFFSET 0x5C + +#define DDATA_OFFSET 0x60 +#define DDIR_OFFSET 0x64 +#define DMASK_OFFSET 0x68 +#define DSTAT_OFFSET 0x6C +#define DEDGE_OFFSET 0x70 +#define DCLR_OFFSET 0x74 +#define DPOL_OFFSET 0x78 +#define DEN_OFFSET 0x7C + +#define EDATA_OFFSET 0x80 +#define EDIR_OFFSET 0x84 +#define EMASK_OFFSET 0x88 +#define ESTAT_OFFSET 0x8C +#define EEDGE_OFFSET 0x90 +#define ECLR_OFFSET 0x94 +#define EPOL_OFFSET 0x98 +#define EEN_OFFSET 0x9C + +#define TICTMDR_OFFSET 0xA0 +#define BMULSEL_OFFSET 0xA4 + +#define GPIO_ADATA (GPIO_BASE + ADATA_OFFSET) +#define GPIO_ADIR (GPIO_BASE + ADIR_OFFSET) +#define GPIO_AMASK (GPIO_BASE + AMASK_OFFSET) +#define GPIO_ASTAT (GPIO_BASE + ASTAT_OFFSET) +#define GPIO_AEDGE (GPIO_BASE + AEDGE_OFFSET) +#define GPIO_ACLR (GPIO_BASE + ACLR_OFFSET) +#define GPIO_APOL (GPIO_BASE + APOL_OFFSET) +#define GPIO_AEN (GPIO_BASE + AEN_OFFSET) + +#define GPIO_BDATA (GPIO_BASE + BDATA_OFFSET) +#define GPIO_BDIR (GPIO_BASE + BDIR_OFFSET) +#define GPIO_BMASK (GPIO_BASE + BMASK_OFFSET) +#define GPIO_BSTAT (GPIO_BASE + BSTAT_OFFSET) +#define GPIO_BEDGE (GPIO_BASE + BEDGE_OFFSET) +#define GPIO_BCLR (GPIO_BASE + BCLR_OFFSET) +#define GPIO_BPOL (GPIO_BASE + BPOL_OFFSET) +#define GPIO_BEN (GPIO_BASE + BEN_OFFSET) + +#define GPIO_CDATA (GPIO_BASE + CDATA_OFFSET) +#define GPIO_CDIR (GPIO_BASE + CDIR_OFFSET) +#define GPIO_CMASK (GPIO_BASE + CMASK_OFFSET) +#define GPIO_CSTAT (GPIO_BASE + CSTAT_OFFSET) +#define GPIO_CEDGE (GPIO_BASE + CEDGE_OFFSET) +#define GPIO_CCLR (GPIO_BASE + CCLR_OFFSET) +#define GPIO_CPOL (GPIO_BASE + CPOL_OFFSET) +#define GPIO_CEN (GPIO_BASE + CEN_OFFSET) + +#define GPIO_DDATA (GPIO_BASE + DDATA_OFFSET) +#define GPIO_DDIR (GPIO_BASE + DDIR_OFFSET) +#define GPIO_DMASK (GPIO_BASE + DMASK_OFFSET) +#define GPIO_DSTAT (GPIO_BASE + DSTAT_OFFSET) +#define GPIO_DEDGE (GPIO_BASE + DEDGE_OFFSET) +#define GPIO_DCLR (GPIO_BASE + DCLR_OFFSET) +#define GPIO_DPOL (GPIO_BASE + DPOL_OFFSET) +#define GPIO_DEN (GPIO_BASE + DEN_OFFSET) + +#define GPIO_EDATA (GPIO_BASE + EDATA_OFFSET) +#define GPIO_EDIR (GPIO_BASE + EDIR_OFFSET) +#define GPIO_EMASK (GPIO_BASE + EMASK_OFFSET) +#define GPIO_ESTAT (GPIO_BASE + ESTAT_OFFSET) +#define GPIO_EEDGE (GPIO_BASE + EEDGE_OFFSET) +#define GPIO_ECLR (GPIO_BASE + ECLR_OFFSET) +#define GPIO_EPOL (GPIO_BASE + EPOL_OFFSET) +#define GPIO_EEN (GPIO_BASE + EEN_OFFSET) + +#define GPIO_TICTMDR (GPIO_BASE + TICTMDR_OFFSET) +#define GPIO_BMULSEL (GPIO_BASE + BMULSEL_OFFSET) + +/* +// GPIO PORT A Enable Register (AEN) +*/ +#define GPIO_AEN_PORTA11 (1 << 11) +#define GPIO_AEN_PORTA10 (1 << 10) +#define GPIO_AEN_PORTA9 (1 << 9) +#define GPIO_AEN_PORTA8 (1 << 8) +#define GPIO_AEN_PORTA7 (1 << 7) +#define GPIO_AEN_PORTA6 (1 << 6) +#define GPIO_AEN_PORTA5 (1 << 5) +#define GPIO_AEN_PORTA4 (1 << 4) +#define GPIO_AEN_PORTA3 (1 << 3) +#define GPIO_AEN_PORTA2 (1 << 2) +#define GPIO_AEN_PORTA1 (1 << 1) +#define GPIO_AEN_PORTA0 (1 << 0) + +/* +// GPIO PORT A De-Bounce Enable Register (ADEBOU) +*/ +#define GPIO_ADEBOU_PORTA11 (1 << 11) +#define GPIO_ADEBOU_PORTA10 (1 << 10) +#define GPIO_ADEBOU_PORTA9 (1 << 9) +#define GPIO_ADEBOU_PORTA8 (1 << 8) +#define GPIO_ADEBOU_PORTA7 (1 << 7) +#define GPIO_ADEBOU_PORTA6 (1 << 6) +#define GPIO_ADEBOU_PORTA5 (1 << 5) +#define GPIO_ADEBOU_PORTA4 (1 << 4) +#define GPIO_ADEBOU_PORTA3 (1 << 3) +#define GPIO_ADEBOU_PORTA2 (1 << 2) +#define GPIO_ADEBOU_PORTA1 (1 << 1) +#define GPIO_ADEBOU_PORTA0 (1 << 0) + +/* +// GPIO PORT B Enable Register (BEN) +*/ +#define GPIO_BEN_PORTB27 (1 << 27) +#define GPIO_BEN_PORTB26 (1 << 26) +#define GPIO_BEN_PORTB25 (1 << 25) +#define GPIO_BEN_PORTB24 (1 << 24) +#define GPIO_BEN_PORTB23 (1 << 23) +#define GPIO_BEN_PORTB22 (1 << 22) +#define GPIO_BEN_PORTB21 (1 << 21) +#define GPIO_BEN_PORTB20 (1 << 20) +#define GPIO_BEN_PORTB19 (1 << 19) +#define GPIO_BEN_PORTB18 (1 << 18) +#define GPIO_BEN_PORTB17 (1 << 17) +#define GPIO_BEN_PORTB16 (1 << 16) +#define GPIO_BEN_PORTB15 (1 << 15) +#define GPIO_BEN_PORTB14 (1 << 14) +#define GPIO_BEN_PORTB13 (1 << 13) +#define GPIO_BEN_PORTB12 (1 << 12) +#define GPIO_BEN_PORTB11 (1 << 11) +#define GPIO_BEN_PORTB10 (1 << 10) +#define GPIO_BEN_PORTB9 (1 << 9) +#define GPIO_BEN_PORTB8 (1 << 8) +#define GPIO_BEN_PORTB7 (1 << 7) +#define GPIO_BEN_PORTB6 (1 << 6) +#define GPIO_BEN_PORTB5 (1 << 5) +#define GPIO_BEN_PORTB4 (1 << 4) +#define GPIO_BEN_PORTB3 (1 << 3) +#define GPIO_BEN_PORTB2 (1 << 2) +#define GPIO_BEN_PORTB1 (1 << 1) +#define GPIO_BEN_PORTB0 (1 << 0) + +/* +// GPIO PORT C Enable Register (CEN) +*/ +#define GPIO_CEN_PORTC15 (1 << 15) +#define GPIO_CEN_PORTC14 (1 << 14) +#define GPIO_CEN_PORTC13 (1 << 13) +#define GPIO_CEN_PORTC12 (1 << 12) +#define GPIO_CEN_PORTC11 (1 << 11) +#define GPIO_CEN_PORTC10 (1 << 10) +#define GPIO_CEN_PORTC9 (1 << 9) +#define GPIO_CEN_PORTC8 (1 << 8) +#define GPIO_CEN_PORTC7 (1 << 7) +#define GPIO_CEN_PORTC6 (1 << 6) +#define GPIO_CEN_PORTC5 (1 << 5) +#define GPIO_CEN_PORTC4 (1 << 4) +#define GPIO_CEN_PORTC3 (1 << 3) +#define GPIO_CEN_PORTC2 (1 << 2) +#define GPIO_CEN_PORTC1 (1 << 1) +#define GPIO_CEN_PORTC0 (1 << 0) + +/* +// GPIO PORT D Enable Register (DEN) +*/ +#define GPIO_DEN_PORTD24 (1 << 24) +#define GPIO_DEN_PORTD23 (1 << 23) +#define GPIO_DEN_PORTD22 (1 << 22) +#define GPIO_DEN_PORTD21 (1 << 21) +#define GPIO_DEN_PORTD20 (1 << 20) +#define GPIO_DEN_PORTD19 (1 << 19) +#define GPIO_DEN_PORTD18 (1 << 18) +#define GPIO_DEN_PORTD17 (1 << 17) +#define GPIO_DEN_PORTD16 (1 << 16) +#define GPIO_DEN_PORTD15 (1 << 15) +#define GPIO_DEN_PORTD14 (1 << 14) +#define GPIO_DEN_PORTD13 (1 << 13) +#define GPIO_DEN_PORTD12 (1 << 12) +#define GPIO_DEN_PORTD11 (1 << 11) +#define GPIO_DEN_PORTD10 (1 << 10) +#define GPIO_DEN_PORTD9 (1 << 9) +#define GPIO_DEN_PORTD8 (1 << 8) +#define GPIO_DEN_PORTD7 (1 << 7) +#define GPIO_DEN_PORTD6 (1 << 6) +#define GPIO_DEN_PORTD5 (1 << 5) +#define GPIO_DEN_PORTD4 (1 << 4) +#define GPIO_DEN_PORTD3 (1 << 3) +#define GPIO_DEN_PORTD2 (1 << 2) +#define GPIO_DEN_PORTD1 (1 << 1) +#define GPIO_DEN_PORTD0 (1 << 0) + +/* +// GPIO PORT E Enable Register (EEN) +*/ +#define GPIO_EEN_PORTE15 (1 << 15) +#define GPIO_EEN_PORTE14 (1 << 14) +#define GPIO_EEN_PORTE13 (1 << 13) +#define GPIO_EEN_PORTE12 (1 << 12) +#define GPIO_EEN_PORTE11 (1 << 11) +#define GPIO_EEN_PORTE10 (1 << 10) +#define GPIO_EEN_PORTE9 (1 << 9) +#define GPIO_EEN_PORTE8 (1 << 8) +#define GPIO_EEN_PORTE7 (1 << 7) +#define GPIO_EEN_PORTE6 (1 << 6) +#define GPIO_EEN_PORTE5 (1 << 5) +#define GPIO_EEN_PORTE4 (1 << 4) +#define GPIO_EEN_PORTE3 (1 << 3) +#define GPIO_EEN_PORTE2 (1 << 2) +#define GPIO_EEN_PORTE1 (1 << 1) +#define GPIO_EEN_PORTE0 (1 << 0) + + +/* +///////////////////////////////////////////////////////////////////////////////////////// +// TIMER Controller Register +*/ +#define T0BASE_OFFSET 0x00 +#define T0COUNT_OFFSET 0x08 +#define T0STAT_OFFSET 0x0C +#define T0CTRL_OFFSET 0x10 +#define T1BASE_OFFSET 0x20 +#define T1COUNT_OFFSET 0x28 +#define T1STAT_OFFSET 0x2C +#define T1CTRL_OFFSET 0x30 +#define T2BASE_OFFSET 0x40 +#define T2COUNT_OFFSET 0x48 +#define T2STAT_OFFSET 0x4C +#define T2CTRL_OFFSET 0x50 +#define T3BASE_OFFSET 0x60 +#define T3COUNT_OFFSET 0x68 +#define T3STAT_OFFSET 0x6C +#define T3CTRL_OFFSET 0x70 +#define TOPCTRL_OFFSET 0x80 +#define TOPSTAT_OFFSET 0x84 +#define P0COUNT_OFFSET 0xA0 +#define P0WIDTH_OFFSET 0xA4 +#define P0PERIOD_OFFSET 0xA8 +#define P0CTRL_OFFSET 0xAC +#define P0PWMTR_OFFSET 0xB0 +#define P1COUNT_OFFSET 0xC0 +#define P1WIDTH_OFFSET 0xC4 +#define P1PERIOD_OFFSET 0xC8 +#define P1CTRL_OFFSET 0xCC +#define P1PWMTR_OFFSET 0xD0 + +#define TIMER_T0BASE (TIMER_BASE + T0BASE_OFFSET) +#define TIMER_T0COUNT (TIMER_BASE + T0COUNT_OFFSET) +#define TIMER_T0STAT (TIMER_BASE + T0STAT_OFFSET) +#define TIMER_T0CTRL (TIMER_BASE + T0CTRL_OFFSET) +#define TIMER_T1BASE (TIMER_BASE + T1BASE_OFFSET) +#define TIMER_T1COUNT (TIMER_BASE + T1COUNT_OFFSET) +#define TIMER_T1STAT (TIMER_BASE + T1STAT_OFFSET) +#define TIMER_T1CTRL (TIMER_BASE + T1CTRL_OFFSET) +#define TIMER_T2BASE (TIMER_BASE + T2BASE_OFFSET) +#define TIMER_T2COUNT (TIMER_BASE + T2COUNT_OFFSET) +#define TIMER_T2STAT (TIMER_BASE + T2STAT_OFFSET) +#define TIMER_T2CTRL (TIMER_BASE + T2CTRL_OFFSET) +#define TIMER_T3BASE (TIMER_BASE + T3BASE_OFFSET) +#define TIMER_T3COUNT (TIMER_BASE + T3COUNT_OFFSET) +#define TIMER_T3STAT (TIMER_BASE + T3STAT_OFFSET) +#define TIMER_T3CTRL (TIMER_BASE + T3CTRL_OFFSET) +#define TIMER_TOPCTRL (TIMER_BASE + TOPCTRL_OFFSET) +#define TIMER_TOPSTAT (TIMER_BASE + TOPSTAT_OFFSET) +#define TIMER_P0COUNT (TIMER_BASE + P0COUNT_OFFSET) +#define TIMER_P0WIDTH (TIMER_BASE + P0WIDTH_OFFSET) +#define TIMER_P0PERIOD (TIMER_BASE + P0PERIOD_OFFSET) +#define TIMER_P0CTRL (TIMER_BASE + P0CTRL_OFFSET) +#define TIMER_P0PWMTR (TIMER_BASE + P0PWMTR_OFFSET) +#define TIMER_P1COUNT (TIMER_BASE + P1COUNT_OFFSET) +#define TIMER_P1WIDTH (TIMER_BASE + P1WIDTH_OFFSET) +#define TIMER_P1PERIOD (TIMER_BASE + P1PERIOD_OFFSET) +#define TIMER_P1CTRL (TIMER_BASE + P1CTRL_OFFSET) +#define TIMER_P1PWMTR (TIMER_BASE + P1PWMTR_OFFSET) + +/* +// Timer [0,1,2,3] Status Register (T[0,1,2,3]STAT) +*/ +#define TIMER_STAT_ST (1 << 0) + +/* +// Timer [0,1,2,3] Control Register (T[0,1,2,3]CTRL) +*/ +#define TIMER_CTRL_CLKSEL_MASK 0xF0 +#define TIMER_CTRL_BYTE_MODE (1 << 3) +#define TIMER_CTRL_RESET (1 << 2) +#define TIMER_CTRL_REPEAT_MODE (1 << 1) +#define TIMER_CTRL_COUNT_ENABLE (1 << 0) + +/* +// Timer Top-level Control Register (TOPCTRL) +*/ +#define TIMER_TOCTRL_TIMER3_OUT_EN (1 << 9) +#define TIMER_TOCTRL_TIMER2_OUT_EN (1 << 8) +#define TIMER_TOCTRL_TIMER1_OUT_EN (1 << 7) +#define TIMER_TOCTRL_TIMER0_OUT_EN (1 << 6) +#define TIMER_TOCTRL_CLK3 (1 << 5) +#define TIMER_TOCTRL_POWER_DOWN (1 << 4) +#define TIMER_TOCTRL_TIMER_3_INTR_EN (1 << 3) +#define TIMER_TOCTRL_TIMER_2_INTR_EN (1 << 2) +#define TIMER_TOCTRL_TIMER_1_INTR_EN (1 << 1) +#define TIMER_TOCTRL_TIMER_0_INTR_EN (1 << 0) + +/* +// Timer Status Register (TOPSTAT) +*/ +#define TIMER_TOPSTAT_TIMER_3_INTR (1 << 3) +#define TIMER_TOPSTAT_TIMER_2_INTR (1 << 2) +#define TIMER_TOPSTAT_TIMER_1_INTR (1 << 1) +#define TIMER_TOPSTAT_TIMER_0_INTR (1 << 0) + +/* +// PWM [0,1] Control Register (P[0,1]CTRL) +*/ +#define PWM_CTRL_CLKSEL_MASK 0xF0 +#define PWM_CTRL_OUTPUT_INVERT (1 << 3) +#define PWM_CTRL_OUTPUT_ENABLE (1 << 2) +#define PWM_CTRL_RESET (1 << 1) +#define PWM_CTRL_ENABLE (1 << 0) + + +#endif /* _HMS30C7210_H END */ \ No newline at end of file diff -urN u-boot-1.0.0/include/mmc.h u-boot-1.0.0-7210/include/mmc.h --- u-boot-1.0.0/include/mmc.h 2003-06-16 07:40:43.000000000 +0900 +++ u-boot-1.0.0-7210/include/mmc.h 2004-05-24 13:44:19.000000000 +0900 @@ -23,8 +23,10 @@ #ifndef _MMC_H_ #define _MMC_H_ +/* +For SOCA7210 MMC Mode #include - +*/ int mmc_init(int verbose); int mmc_read(ulong src, uchar *dst, int size); int mmc_write(uchar *src, ulong dst, int size); diff -urN u-boot-1.0.0/include/version.h u-boot-1.0.0-7210/include/version.h --- u-boot-1.0.0/include/version.h 2003-10-30 08:18:57.000000000 +0900 +++ u-boot-1.0.0-7210/include/version.h 2004-02-12 09:32:16.000000000 +0900 @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 1.0.0" +#define U_BOOT_VERSION "U-Boot 1.0.0-soca7210-1" #endif /* __VERSION_H__ */ diff -urN u-boot-1.0.0/lib_arm/armlinux.c u-boot-1.0.0-7210/lib_arm/armlinux.c --- u-boot-1.0.0/lib_arm/armlinux.c 2003-07-26 17:08:21.000000000 +0900 +++ u-boot-1.0.0-7210/lib_arm/armlinux.c 2004-05-25 13:24:35.000000000 +0900 @@ -70,7 +70,6 @@ extern image_header_t header; /* from cmd_bootm.c */ - void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { @@ -82,11 +81,12 @@ void (*theKernel)(int zero, int arch); image_header_t *hdr = &header; bd_t *bd = gd->bd; + uint32_t kernel_entry = hdr->ih_ep; #ifdef CONFIG_CMDLINE_TAG char *commandline = getenv("bootargs"); #endif - - theKernel = (void (*)(int, int))ntohl(hdr->ih_ep); + + theKernel = (void (*)(int, int))ntohl(kernel_entry); /* * Check if there is an initrd image @@ -97,14 +97,14 @@ addr = simple_strtoul(argv[2], NULL, 16); printf ("## Loading Ramdisk Image at %08lx ...\n", addr); - + /* Copy header so we can blank CRC field for re-calculation */ #ifdef CONFIG_HAS_DATAFLASH if (addr_dataflash(addr)){ read_dataflash(addr, sizeof(image_header_t), (char *)&header); } else #endif - memcpy (&header, (char *)addr, sizeof(image_header_t)); + memcpy (&header, (char *)addr, sizeof(image_header_t)); if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); @@ -137,7 +137,6 @@ data = CFG_LOAD_ADDR; } #endif - if (verify) { ulong csum = 0; @@ -198,14 +197,19 @@ } #endif - if (data) { - initrd_start = data; + if (data ) { + initrd_start = 0x40200000; initrd_end = initrd_start + len; + + printf (" Loading Ramdisk to %08lx, end %08lx ... ", initrd_start, initrd_end); + memmove ((void *) initrd_start, (uchar *)data, len); + printf ("OK\n"); + } else { initrd_start = 0; initrd_end = 0; } - + SHOW_BOOT_PROGRESS (15); #ifdef DEBUG @@ -225,7 +229,7 @@ setup_commandline_tag(bd, commandline); #endif #ifdef CONFIG_INITRD_TAG - setup_initrd_tag(bd, initrd_start, initrd_end); + setup_initrd_tag(bd, initrd_start, initrd_end); #endif #if 0 setup_ramdisk_tag(bd); @@ -240,7 +244,7 @@ printf("\nStarting kernel ...\n\n"); cleanup_before_linux(); - + theKernel(0, bd->bi_arch_number); } @@ -335,8 +339,8 @@ params->hdr.tag = ATAG_RAMDISK; params->hdr.size = tag_size(tag_ramdisk); - params->u.ramdisk.start = 0; - /*params->u.ramdisk.size = RAMDISK_SIZE; */ + params->u.ramdisk.start = initrd_start; + params->u.ramdisk.size = initrd_end - initrd_start; params->u.ramdisk.flags = 1; /* automatically load ramdisk */ params = tag_next(params); diff -urN u-boot-1.0.0/lib_arm/board.c u-boot-1.0.0-7210/lib_arm/board.c --- u-boot-1.0.0/lib_arm/board.c 2003-10-30 08:18:57.000000000 +0900 +++ u-boot-1.0.0-7210/lib_arm/board.c 2003-11-28 17:43:36.000000000 +0900 @@ -128,7 +128,12 @@ printf ("IRQ Stack: %08lx\n", IRQ_STACK_START); printf ("FIQ Stack: %08lx\n", FIQ_STACK_START); #endif - +#ifdef CONFIG_ARCH_H7202 + printf ("BOOT DEVICE = \n\n"); + printf ("CPU = HMS30C7202 \n\n"); + printf ("Board = hnx7202 version 1.1 \n\n"); +#endif + return (0); } diff -urN u-boot-1.0.0/Makefile u-boot-1.0.0-7210/Makefile --- u-boot-1.0.0/Makefile 2003-10-28 18:14:21.000000000 +0900 +++ u-boot-1.0.0-7210/Makefile 2004-01-26 10:51:59.000000000 +0900 @@ -890,6 +890,9 @@ ep7312_config : unconfig @./mkconfig $(@:_config=) arm arm720t ep7312 +soca7210_config : unconfig + @./mkconfig $(@:_config=) arm hms30c7210 soca7210 + ######################################################################### ## XScale Systems ######################################################################### diff -urN u-boot-1.0.0/rtc/h7210_rtc.c u-boot-1.0.0-7210/rtc/h7210_rtc.c --- u-boot-1.0.0/rtc/h7210_rtc.c 1970-01-01 09:00:00.000000000 +0900 +++ u-boot-1.0.0-7210/rtc/h7210_rtc.c 2004-05-20 10:51:51.000000000 +0900 @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the built-in Hynix HMS30C7210 RTC + */ + +#include +#include + +#if defined(CONFIG_RTC_H7210) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#include +#include + +/* +#define RTC_DEBUG +*/ +static void protect_enable(void) +{ + _outb(RTC_PROTCTRL,0x01); + _outb(RTC_PROTECT1,0xaa); + _outb(RTC_PROTECT2,0x48); + _outb(RTC_PROTECT3,0x61); + _outb(RTC_PROTECTLAST,0x99); +} + +static void protect_disable(void) +{ + _outb(RTC_PROTCTRL,0x00); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year; + uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed; + + /* read RTC registers */ + sec = _inb(RTC_RTCSEC); + min = _inb(RTC_RTCMIN); + hour = _inb(RTC_RTCHOR); + mday = _inb(RTC_RTCDAY); + wday = _inb(RTC_RTCWEK); + mon = _inb(RTC_RTCMON); + year = _inb(RTC_RTCYER); + + _outb(RTC_RTCSTAT,RTC_RTCSTAT_READ_FLAG); + + /* read ALARM registers */ + a_sec = _inb(RTC_ALSEC); + a_min = _inb(RTC_ALMIN); + a_hour = _inb(RTC_ALHOR); + a_date = _inb(RTC_ALDAY); + a_mon = _inb(RTC_ALMON); + a_year = _inb(RTC_ALYER); + a_armed = _inb(RTC_ALCTRL); + +#ifdef RTC_DEBUG + printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec); + printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n", + a_armed, + a_year, a_mon, a_date, + a_hour, a_min, a_sec); +#endif + + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_hour = bcd2bin(hour & 0x3F); + tmp->tm_mday = bcd2bin(mday & 0x3F); + tmp->tm_mon = bcd2bin(mon & 0x1F); + tmp->tm_year = bcd2bin(year); + tmp->tm_wday = bcd2bin(wday & 0x07); + tmp->tm_year+=2000; + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year; + +#ifdef RTC_DEBUG + printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + year = bin2bcd(tmp->tm_year % 100); + mon = bin2bcd(tmp->tm_mon); + wday = bin2bcd(tmp->tm_wday); + mday = bin2bcd(tmp->tm_mday); + hour = bin2bcd(tmp->tm_hour); + min = bin2bcd(tmp->tm_min); + sec = bin2bcd(tmp->tm_sec); + + /* enable access to RTC registers */ + protect_enable(); + + // RTC STOP + _outb(RTC_RTCTRL,_inb(RTC_RTCTRL) | 0x01); + + _outb(RTC_RTCYER,year); + _outb(RTC_RTCMON,mon); + _outb(RTC_RTCDAY,mday); + _outb(RTC_RTCHOR,hour); + _outb(RTC_RTCMIN,min); + _outb(RTC_RTCSEC,sec); + + // RTC START + _outb(RTC_RTCTRL,_inb(RTC_RTCTRL) & ~0x01); + + /* disable access to RTC registers */ + protect_disable(); +} + +void rtc_reset (void) +{ + // Initialize STAT register for Gate-level simulation + _outb(RTC_RTCSTAT,(RTC_RTCSTAT_TICK_FLAG|RTC_RTCSTAT_READ_FLAG|RTC_RTCSTAT_ALM_FLAG)); + + protect_enable(); + // rtc ctrl resetting [1-->0] + _outb(RTC_RTCTRLRESET,RTC_RTCTRLRESET_CTRLRESET); + _outb(RTC_RTCTRLRESET,0x00); + + // Clear RTC counter register reset bit [1-->0] + _outb(RTC_RTCTRL,_inb(RTC_RTCTRL) | RTC_RTCTRL_RESET); + _outb(RTC_RTCTRL,_inb(RTC_RTCTRL) & ~RTC_RTCTRL_RESET); + + // RTC START + _outb(RTC_RTCTRL,_inb(RTC_RTCTRL) & ~0x01); + + protect_disable(); +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_RTC_H7210 && CFG_CMD_DATE */ diff -urN u-boot-1.0.0/rtc/Makefile u-boot-1.0.0-7210/rtc/Makefile --- u-boot-1.0.0/rtc/Makefile 2003-06-20 08:01:53.000000000 +0900 +++ u-boot-1.0.0-7210/rtc/Makefile 2004-05-20 10:17:09.000000000 +0900 @@ -31,7 +31,7 @@ ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \ ds1556.o ds164x.o ds174x.o \ m41t11.o m48t35ax.o mc146818.o mk48t59.o \ - mpc8xx.o pcf8563.o s3c24x0_rtc.o + mpc8xx.o pcf8563.o s3c24x0_rtc.o h7210_rtc.o all: $(LIB)