Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1.Is the 7202 LCD controller identical with the 7201 LCD controller?If it's different, can you please describe the main difference? A1.7202A has the same LCD controller but palette size were changed (12bpp in 7201, 7202A has 16 bpp palette) so some registers have changed a little bit.(removed VGA part, expanded palette register) And the data sheet is also identical except changed part and removed VGA controller part. Q2.According to the datasheet the maximal LCD resolution is 640x480. But the internal registers structure seemed to be able to support up to 1024x1024. (LCD Timing 0 Register allows up to 1024 pixels per line, LCD Timing 1 Register allows up to 1024 lines in frame) What prevents to use resolutions up to 1024xX? A2.Simply speaking, 7202 has not enough internal system bus bandwidth and LCD PLL clock frequency to deal with more than 640x480 display properly.And 7202 is not tested to support more than 640x480 resolution. Q3.In color STN mode, how are the pixels mapped to the LD[7..0] output pins? Are the first (leftmost) pixels in the least or most significant LD bits? A3.Here's answer for normal case usage(not swap color) In mode STN mode, the low order LD signals are the first pixels on the line, and the high order LD signals are later pixels on the line. In color mode things are different once again. LD[7] is the red component of the first pixel on the line, and LD[6] is the green component of the pixel, and LD[5] the blue, with LD[4] being the red component of the next pixel. This pattern continues, with LD[0] being the green component of the third pixel, and LD[7] of the next clock being the blue component of the same pixel. This is shown diagrammatically below. Time ----------------------------------------> LD[7]  R(0)  LD[7]  B(2)  LD[7]  G(5)  LD[7]  R(0) LD[6]  G(0)  LD[6]  R(3)  LD[6]  B(5)  LD[6]  G(0) LD[5]  B(0)  LD[5]  G(3)  LD[5]  R(6)  LD[5]  B(0) LD[4]  R(1)  LD[4]  B(3)  LD[4]  G(6)  LD[4]  R(1) LD[3]  G(1)  LD[3]  R(4)  LD[3]  B(6)  LD[3]  G(1) LD[2]  B(1)  LD[2]  G(4)  LD[2]  R(7)  LD[2]  B(1) LD[1]  R(2)  LD[1]  B(4)  LD[1]  G(7)  LD[1]  R(2) LD[0]  G(2)  LD[0]  R(5)  LD[0]  B(7)  LD[0]  G(2)