Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1. What it purpose of the Sleep mode? A1. Sleep mode is only a intermediate step to enter the DeepSleep. Q2. What needs to be done for a Wake-up?Is it a RESET? Or Interrupt? If it's an Interrupt, is it correct that the registers content is maintained? A2. External interrupts and RTC can make wake-up, nRESET also wake up HMS30C7202 but in this case registers are cleared with default value.After wake-up with external or RTC event, registers contents are maintained. Q3. The state diagram shows that the wakeup from DeepSleep goes to Sleep mode and then IDLE. Is it possible to go from Sleep to Slow or Run?Can this be programmed? A3. No, user can not program from sleep mode to slow mode, because HMS30C7202 can not stay in sleep mode. (from Q1/A1) Wake-up sequences from deep sleep mode would be end at SLOW not IDLE, user can find "WakeUp event" make state machine goes to SLOW from DEEPSLEEP Q4. What software requirements are needed before entering Sleep or DeepSleep mode? A4. Please see below about "I. General Informations …" Q5. On the 7202 datasheet, the pin 38, 39 and 40 belong to PLL1, pin 42, 43 and 44 belong to PLL0, Pin 41 belongs to PLL2. Which PLL is the system clock ? Which PLL is the LCD clock ? Which PLL is the CCLK(USB, CAN) clock? A5. pin no. 43 PLLFILT[0] is filter pin of PLL1 function(LCD PLL), pin no. 39 PLLFILT[1] is connected with PLL2 (USB, CAN) block and no. 41 PLLFILT[2] pin is related with PLL3(System PLL).Three PLL blocks have just two fair of power pins(VDD/VSS). PLL1(LCD), PLL3(SYSTEM) are made with the same PLL IPs , so we made these two PLLs use single power. These PLL are using PLLVDD[0], PLLVSS[0] together; pin 42, 44. PLL2(USB,CAN) is fixed 48 MHz PLL, we separate power for this PLL from others to prevent noise problem. PLLVDD[1], PLLVSS[1]; pin 38, 40. Q6.It is targeting to minimize the system power consumption by reducing the clock frequency and active time of the SDRAM (LCD).The data book shows a minimum frequency of about 50MHz. But I wants to use the lowest possible clock frequency. Can you tell me all possible settings? A6. CPU PLL designed and verified only for about 40-100MHz range. We also supposed one bit of PLL clock setting corresponds x0.5 multiplication factor of PLL input clock. (There's a register for multiplication factor inside PLL) So user can try to set lower clock than datasheet, but we can not assure stability of PLLs. Q7. Could you please tell me the states of the I/O and KSCAN pins, if the H7202 is going to "sleep" or "deep sleep mode" (Tri-state, last state, ...)? A7.It remembers the last state. Q8.[FAQ]General Informations for Deep-sleep, Wake-up Issues of HMS30C7202 PMU A8. (1) Wake-up A. HMS30C7202 has four external wake-up sources, and one of two power condition pins(PMADAPOK, PMBATOK) should be high. MRING(nURING), nPMWAKEUP, RTC event can not be masked. PMU only has interrupt mask bits for interrupt controller. It means even though 7202 wake-up from deep-sleep, there might be no interrupt for interrupt controller. But every time, HMS30C7202 would wake up, when any one of wake-up sources asserted. i. Wake-up sources MRING : It's connected nURING pin ("n" of nURING pin means "low active") This signal can not be masked in PMU. HOTSYNC : HotSync condition or user defined condition(ex. Plugging power adaptor). This signal is connected with GPIOB[10] interrupt. nRESET : nRESET signal wake up from deep-sleep. PMWAKEUP : low active external signal. This signal can not be masked. RTC Event : from RTC. This signal is not makable in PMU. All wake-up sources are filtered by debounce circuit with 250Hz clock from RTC clock, so if RTC clock stopped, wake-up sequence would not work. ii. Needed condition for wake-up One of PMADAPOK and PMBATOK should be high, it means there's no power problem.If user want to make wake-up regardless power source condition, set "WAKEUP" bit of PMU Mode register(PMUMODE) bit[3]. (2) Deep-sleep A. To go deep-sleep state, all wake-up conditions are cleared. If any wake-up pin stay in wake-up condition, 7202 would not go into "deep-sleep mode". B. Once Deep-sleep mode is set(in Slow mode) and no wake-up signal condition, State machine wait until Bus Idle state. And after state machine jump into Bus Idle, in the very next "bus access" operation, PMU get bus mastership from CPU and state machine keep going into deep-sleep mode through short sleep state.Sometimes S/W need to wait until Bus Idle(ex. DMA cases) and to prevent un-wanted the next instruction execution after deep-sleep instruction set PMU Mode Register(PMUMODE), usually dummy loop is used for this purpose. C. In some cases(in some S/W), to keep going into deep-sleep, dummy bus(ex. Just single read of a peripheral register) access is helpful after dummy loop. We think it related with changing bus mastership.(or may need longer dummy loop)