Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1. SCLK is FCLK (70MHz)? A1. Yes, SCLK is FCLK. Q2. If auto-precharge is disabled (SCDON A=0), does the SDRAM controller then generate precharge commands as necessary? Is there any reason why I would want to disable auto-precharge? It looks like it is better to use auto-precharge, right? A2. If auto-precharge is enabled, SDRAM controller issues "Read/Write with Auto-Precharge" command instead of normal "Read/Write" command.So, SDRAM controller generates "Active" command before each Read/Write operation.If auto-precharge is disabled, SDRAM controller uses normal "Read/Write" command and SDRAM page that is accessed before remains active. So, SDRAM Controller issues "Pre-charge" command only in the case that One SDRAM page is active and there is need to read/wirte the other page address in the same bank.You had better disable auto-precharge bit, if a number of SDRAM accesses occur in the same page boundary - You can perform SDRAM "Read/Write" command fast without "Pre-charge" & "Active" command. Q3. There is almost no timing parameter of the SDRAM controller in the datasheet, and only very little adjustment is possible. Things like read to write, consecutive read or write bursts etc. are not specified. So it is impossible for me to check if the CPU will meet all the SDRAMs specifications, and if there are problems, it will not be possible to correct them in software with adding additional cycles. Can you guarantee that the CPU will work with the above mentioned SDRAMs? A3. Yes, We can guarantee that SDRAM controller meet the timing. Q4. Burst length: The CPU datasheet says on ch.6: "Video accesses to the SDRAM occur in fixed-burst lengths of 16 words. ARM and DMA controller accesses occur in a fixed-burst length of four words." Word is 32 bit. This means that video accesses are 32 x 16 bit, and ARM+DMA 8 x 16 bit. So there are 4 consecutive read bursts for each video access? Or does the controller use full page bursts? A4. At each Video access, SDRAM controller issues 4 consecutive "Read" commands of which burst length is 8 half-word. So, if you want to get the successive 16 words,the start address of SDRAM read must be arranged to 4-Word(8-HalfWord) boundary - The start address of SDRAM must be 0xXXXX_XXX0. But ARM/DMA Access SDRAM Controller discards the data of which the address is not sequentially increased. For example, If ARM do the 4-Word "ldm(load Block data)" of which start address is 0x4000_0004, the Address output from SDRAM Controller to SDRAM is start from 2 (just 4bits from LBS). SDRAM do the 8-HalfWord Burst Read and it's address sequence is 2-3-4-5-6-7-0-1. In that case, SDRAM Controller discards data from address 0,1 and just get the 6-HalfWardData (Address from 2 to 7). After that, SDRAM Controller issue the "Read" Command again of which Start address to SDRAM is 8 and gets the 2-HalfWord data(data from SDRAM address 8,9). Q5. See chapter 6: "Supports 2/4 banks with page lengths of 256 or 512 half words". If so, how does it know the SDRAM's page size? A5. SDRAM Controller does not know the SDRAM's page size, but you can use 256 and 512-Page device both.Table 6-2 on ch.6.4 shows the relationship between "SDRAM Row/Col Address" and internal Address of 7202. At that table, SDRAM Column Address 8 is mapped to internal address 23.SDRAM which has 256-page size does not use Column Address 8.If you use the 256-HalfWord device, SDRAM ignores the Column Address 8.So, SDRAM Controller access the same SDRAM address location in the case that ARM/DMA access 0x4080_0000 and 0x4000_0000.If you use the 512-HalfWord device, SDRAM does not ignore the Column Address 8.So, SDRAM Controller access the other SDRAM column address location in the case That ARM/DMA access 0x4080_0000 and 0x4000_0000. Q6. SDRAM mode register (in the SDRAM, not SDCON) How this register must be initialized? A6. - Write Burst Mode = "Programmed Burst Length" - Burst Type = "Sequential" - Burst Length = 8 Q7. Base address of SDRAM 0 Memory Map Table 4-1: base address = 1024 MByte = 0x4000.0000 ch.6.2.1 SDCON register Bit 3: "1 = a device is present at address range 0-32MByte" Shouldn't it be 1024-1056MByte? A7. Yes, you are right.It should be "1024-1056(1024+32)MByte" Q8. Referring to the figures in "12.5.2 SDRAM Interface" Q8-1. RAS/CAS Timing:The 42ns are 3xSCLK ? Is 3x fixed or does it depend on any other parameter? A8-1. Yes it is fixed to 3xSCLK. Q8-2. All timing diagrams:Shouldn't RAS and CAS go high again after 1 SCLK (-> NOP command)? RAS+CAS low is auto/self refresh command, and with WE low it's load mode register command, or am I wrong? A8-2. Yes, RAS and CAS should go high again after 1-SCLK. The purpose of this figure is to show only timing between the SDRAM signals- RAS,CAS,WE, and DataIn/Out, but that's not correct in the respect to SDRAM function. Q8-3. Single/Burst Read Operation:The 42-46ns is 3xSCLK. Is this with programmed CAS latency=3 ? Yes The SDRAM supports CAS latency=2 at max 100MHz. So it should be no problem to use CAS latency=2 (SDCON C[1:0]=10) with 70MHz.Do you expect any problems? A8-3. No, there is no problem at using "CL=2".You can use SDRAM at "CL=2" by setting SDRAM mode register and SCDON. Q8-4. Single Read/Write: Does the SDRAM controller perform single accesses at all? A8-4. SDRAM Controller can perform single Word/HalfWard/Byte Read/Write, if ARM/DMA request the SDRAM access. Q9. How to connect the SDRAM's address lines(64MBit, 16M x 16) to the CPU? A9. SDRAM A[11:0] = CPU SA[11:0] SDRAM BA1 = CPU SA12/BS1 SDRAM BA0 = CPU SA13/BS0 Q10. If the SDRAM controller handles all this, I will of course use the faster mode and disable auto precharge.So the SDRAM controller issues a PRECHARGE command automatically whenever it is necessary?It outputs the auto precharge control bit on SA10? A10. Yes, Yes Q11. In "12.5.2 SDRAM Interface", there are figures for "Single Read Operation" and "Single Write Operation". Because the SDRAM controller makes only 8-halfword burst accesses, I wonder why there are these figures. When does the CPU make this "Single Read/Write Operation"? A11. This figure does not describe the timing of SDRAM Controller but the SDRAM timing parameter. Q12. Read access: when does the SMI latch the input data? A12. When BWAIT is LOW and BCLK is negedge, valid RD is latched. Therefore, the input data latched in the tHO(D).(ch.12.5.1.1) Q13. When does CS goes LOW? When the address is put on the bus (figures in 12.5.1) or one BCLK after the address (figures in 7.4)? This makes one BCLK difference for the waitstates. A13. RA is latched address from BA. After one BCLK , nRCS goes to LOW(ch.7.4). But, The WAITSTATES is NOT DIFFERENCE to one BCLK.In case of the waitstates, Looks like non-exact wait value. Exactly, wait counter is start to wait counting after RA latched next one-BCLK. So, Waitstate value is NOT LOSS any case. Q14. What is the difference between "7.4.2 read normal wait (sequential)" and "7.4.3 read burst wait (sequential)" from the memory's view? (Q14-1) If the figures are correct, the memory sees no difference between normal sequential and burst sequential, except that for burst the first cycle can have different timing. This means that sequential accesses are always burst, even if burst is disabled (see 7.4.2). Is this true? (Q14-2) I think I can use burst read wait=3 and normal access wait=4, exactly like in 7.4.3:for the 1st access, nRCS active to data latch is 4xBCLK, and for the following accesses RA change to data latch is also 4xBCLK. Is this correct? (Q14-3) A14-1. Normally, it set to Fast performance memory device(i.e. Internal accelerator exist to Read Only Memory(e.g. Strata FLASH needs time to wait in the first access and the other wait is no more long waits. if burst read set.)) has useful BURST READ WAIT STATE. Generally, NORMAL WAIT STATE makes use of SRAM. A14-2. Actually, this question is confused. In the ch.7.4.2 and 7.4.3 are different to Mode(Burst or Normal). The principles of sequence access mean that the address is sequential. If the AMBA signals(BA, BTRAN, BWAIT, etc) give to the internal controller for burst operation, the controller gives to external memory to need for operation. A14-3. The first access case, BTRAN needs to 1-cycle address only commend. it's MBA provision. So, You look like more 1xBCLK wait in the First access. RA is only latch to BA.therefore, in this figure 7.4.3 , the first access part always 4xBCLK likes NORMAL WAITSTATE. Q15. The problem is about the MMC Response Buffer Register (0x8001.5048). I couldn't write or erase it. Also a reset didn't change the value.It only changes the value after a power down (then it assumes another- random -value). Can it be modified? How? A15. There is no way to write the MMC Response Buffer directly.This Register can be written only when the Response from MMC Card is received.