Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1. The 7202 has pins for 4 UARTs + IrDA.But I think we cannot use 4 UARTs + IrDA.One UART is internally used for IrDA (if activated). Is this right ? A1.Yes, you are right. The UART 1 used as IrDA. Q2. CAN module can set NIRQ - this is the same as the NIRQ from the int. cntr. ? (CAN is the only peripheral which can set the NIRQ) A2.CAN controller also make NIRQ via Interrupt controller(likes others) But CAN controller has own enable bit to make interrupt signal. (It also likes other peripherals) This signal use to inform "a CAN interrupt occured" to Interrupt controller.To make a NIRQ, an interrupt signal should be transfer to "Interrupt controller" from "CAN controller". But both CAN controller and Interrupt controller has own "enable bit". So user should set "1" Interrupt enable bit in both controller. Q3. 10.2.3.1. CAN control register, Bit 1 Module Interrupt Enable '1': Enabled - Interrupt will set NIRQ to LOW. NIRQ remains LOW until all pending interrupts are processed. '0': Disabled - Module Interrupt NIRQ is always HIGH 10.4. Interrupt controller The Interrupt controller can trigger ....the standard interrupt request (NIRQ) ...Is the NIRQ ORed? A3. - For the 10.2.3.1, it means CAN interrupt make NIRQ(NIRQ is active low signal for ARM720T), but this time Interrupt enable register(IER) bit[19] or [18] of "interrupt controller" should be set "1". (If IER bit [19] and [18] set to be "0", NIRQ would never occur for CAN controller, even though CAN controller make an interrupt.) And this interrupt signal stay till CPU read CAN status register. After read CAN status register in CAN controller, CAN interrupt will be clear and NIRQ also will be removed . And "NIRQ is always HIGH" means there's no CAN interrupt for CPU. This "module interrupt enable" bit is a sort of "master" CAN interrupt enable bit. If you wanted to make an interrupt from CAN controller, you should make this bit set "1". In other words, this bit could be called as "interrupt Mask" when "1" CAN interrupt signal pass to "interrupt controller", when "0" CAN interrupt signal will not pass. - For the 10.4 It can not be simply explained as "AND" or "OR", above answer can be helpfull to understand your problem. We think your problem mainly caused from "NIRQ goes LOW". Q4.what is the max speed (kbit/s) of the SPI ? A4. The max speed of SPI is descibed in datasheet chapter 9.2.2.1.If you use 80MHz cpu speed, max speed is 20 MHz. Q5. If PLL is disabled, can the clock be generated by an ext. quarz (e.g. 20 MHz) or is it necessary to input a digital clock ? Which value has FCLK if we use 20MHz quartz (20MHz inout clock) ?Please confirm that the clockin is OSCIN (pin29). A5. We think it's not a good idea of using external lower clocks.The reason is like that, we just thought about "the worst case" of PLLs and using for "chip test" of mass production with nPLLENABLE pin, and internally 7202 use 5 sorts of clocks FCLK, QFCLK (1/4 phase delayed FCLK), PCLK(3.6864 MHz), BCLK(1/2 FCLK), LCLK(LCD), CCLK(48MHz) ARM720T needs 1/4 phase delayed CPU clock (I think it used to solve timing problem of internal bus transfer with BCLK) and FCLK, QFCLK, BCLK, LCLK, CCLK have own path when nPLLENABLE is high. Please see chapter 2.2.2.2 PORTB (Normal bypass), and also OSCIN needs 3.6864 Mhz for PCLK. All above clocks need to be digital clocks except PCLK (PCLK goes OSCIN pad, it's an oscillator pad) Q6. The 7202 has four UARTs, but only UART0 is a full UART with all the MODEM signals (CTS, RTS, DSR, DTR, RI and DCD). We want to implement hardware flow control with UART1, and for that purpose we use some IOs. Once we detect the signals we try to change the corresponding values in the MSR (UART1) register, but I think we can not change that register. Could you tell us if that register is a R/W register? A6. There is no way to write the MSR directly by software. We think that you had better SCR register for that purpose. SCR register is R/W register and can be used to hold temporary value by the program. Q7.Is there a way to set device description manufacturer / model (human readable) strings? Based on the documentation I was able to find ways to change device manufacturer and model ID's (DEVID). Moreover, 9.6.1 Block Diagram (USB block diagram in above-mentioned .pdf) refers to "Configuration Rom" containing "Device Descriptor", does this mean that device desciptor is fixed by MagnaChip? A7. There is a mostly Hard-wired(fixed) device ROM in USB device controller of 7202. That contains Descriptors of this USB function block. So when there comes a Get Descriptor Request from HOST, the content of this ROM will be sent to HOST. BUT there are 3 changable value fields in this ROM (not fixed).These addresses are mapped to writable registers. I write down the ROM table below, and you can find fields tailed by 7 *'s(*******).There are two 24-bit fields in device descriptor, and one 32bit field in config. descriptor.You can find what address you should write to modify these values in our spec.There are 3 registers, DEVID, DEVCLASS and INTCLASS corresponding respectively. Q8. What is necessary to power down the USB block ? A8. I think this matter might relate with USB transceiver block. USB transceiver goes suspend mode by itself, without USB signal activity for 3 ms. But for this, user have to be enable USB block and PLL2.If USB function did not work at least once before going to deep-sleep, USB transceiver could not go suspend mode. So additional codes may need to go to power down include USB transceiver in this case. try the sequence below (1) PLL2 enable ; set bit[15] of PMU clock control register : address 0x80001028 (2) USB enable ; make full power operation mode write "0x10" into USB PWR register: address 0x80012010) (3) wait about 3 ms without USB activity.(I recommend some more time to make sure, or try to check analog power      changing at this moment) (4) PLL2 disable ;clear bit[15] of PMU clock control register