Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1. What is the exact state of multi function IO pins during and after nRESET?It is clear that the primary function is active (xEN = 0x0000) and the ports are inputs (xDIR = 0xFFFF). This can be seen in the tables in chapter 2.2.2.But for some ports the primary function is output, not input. Example:After reset, Port A is "Primary", which is KSCANO0..7 and KSCANI0..7. For KSCANO0..7, the table on p. 20 is empty in the "Input" column.So what is the reset state of KSCANO0..7: input (because ADIR=0xFFFF), or output (because it is "Primary", and Primary is output)? A1. After reset, ports are assigned for Primary functions. In this case GPIO port direction register have no meaning for the primary functions each ports have their own directions. Q2. Does the port function setting with xEN override the xDIR setting? In other words: if I set e.g. PORTB1 to "Primary" (nUDTR), is it then automatically set to "Output", no matter how the BDIR setting is?Or again in other words: if I select a port function (Primary or Multifunction, not GPIO) which has a clear direction, must I to set the xDIR bit anyway? A2. No, you don't need to control xDIR, xDIR registers only affect for GPIO functions(when GPIO is enable). Q3. ADATA after a reset(ch.10.3.2.1): "All bits are cleared by a system reset".And: "On reads, the Data Register contains the current status of correspondent port pins, whether they are configured as input or output".But after reset, all pins are inputs, so reading them should return the input state,which is not necessarily 0. What is true? A3. All Data register bits can be written under any GPIO conditions.But this value could not be read directly. Because when user try to read ADATA register, external pin status(value) will come in directly(this value is not a value in Data register). If user wanted to read the value of Data register that was written before, user should have to enable GPIO function and set direction as output then data register value could be read from ADATA register address. Simply, user writes into 16-bit Data register, but read from external pins with the same address. Q4. If I write to ADATA while a port is set as input, is the written value latched? The reason for this question: I want to program a GPIO port for output and start with a H output level without any L glitch.There is a pull-up on the port.I think because ADATA is 0x0000 after reset, the port will be L when I enable GPIO and set ADIR for output. So the better way would be: first set the port bit in ADATA to 1, and then set the port to GPIO and ADIR for output. But: "Writing to a Data Register only affects the pins that are configured as outputs". Does this mean that writing has no effect at all, or is there an output latch which keeps this value until the port becomes actually an output? A4. Data register keeps previous value until GPIO enable.But user may have different value with writing value when user try to read this register.(from answer for the question 3) Q5. APOL(ch.10.3.2.7): "After accessing this register, the Edge Mode register should be cleared with the Clear register."Does "access" mean read and write? Or only write ("After writing to this register,....")?Is it correct that the Clear register (ACLR?) clears the Edge Mode register (AEDGE?), not ASTAT? AEDGE makes no sense to me.If I have to clear the interrupt after writing to this register, shouldn't I better disable the interrupt in AMASK before writing to APOL? Otherwise, an interrupt will occur when I write to APOL. But if I disable the interrupt, the bit in ASTAT will never be set "(masked interrupt is always 0)". So why do I have to reset ASTAT? A5. ACLR register is used to clear ASTAT register.APOL value is operated "XOR" with input signal to make interrupt. So in some cases, APOL writing causes interrupt occurring.I think, you'd better disable AMASK register before writing APOL register. Q6. APOL(ch.10.3.2.7): does the APOL setting also have effect in edge mode? A6. AEDGE=1 and APOL=1 -> negative edge AEDGE=1 and APOL=0 -> positive edge