Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION [LCD] Q1. [LCD]What kind of display does 7202 reference board support? A1. - LCD STN Color (640 x 480) - LCD STN Mono (640 x 480) - LCD TFT Color (640 x 480) Q2. [LCD]How should I connect the mono LCD data lines ? A2. The LCD data lines of 7202 are twisted. The connection should be as follows. LCD   7202 D0     LD2 D1     LD3 D2     LD0 D3     LD1 (But STN & TFT color LCDs data lines are not twisted.) [PS2] Q3. [PS2]Does the PS2 interface support two PS2 devices connected at the same time? Could it be done by SW changes? A3. 7202 Reference board supports only 1 PS2 port. You can use it for keyboard, mouse.... any other P/S2 devices. But you can't use 2 devices at the same time. If You want to use 2 devices at the same time, you should make 2 PS ports at 1 PS2 interface and control it with GPIO port. [MMC] Q4. [MMC]The Multimedia Card supports SPI Interface. Will it be possible for you to comment as to how this interface is different from the standard 7 wire MMC interface ? What might be the implication of this interface as compared to the standard MMC Interface ? A4. Please refer to MMC specification fo sandisk web-site. [SDRAM] Q5. [SDRAM]Is the SDRAM bus frequency always the half of FCLK? A5. Yes. SDRAM bus frequency is always the half of FCLK.External SDRAM interface uses the same frequency as FCLK. [MMU] Q6. [MMU]Regarding the encache.c-file and initMMU: - The MMU and cache seems not to be enabled in case of ARM720T (via the enable function).    Why? What is the command to enable them? Compare to the other processors! - Do we have to make other adjustions in case of ARM720T ? - Can we use encache.c file in our project despite the "copyright" ? A6. I don't know about encache.c. Sorry about it. However you need to check it is for ARM720T. I think maybe it's not for ARM720T. So please read carefully the comment in 'encache.c' to check it [PMU] Q7. [PMU]What is the max speed of 7202 ? A7. Maximum guarantee speed is 70MHz. Q8.[PMU]What it purpose of the Sleep mode ? A8. Sleep mode is only a intermediate step to enter the Deep Sleep. Q9. [PMU]What needs to be done for a Wake-up? Is it a RESET? or Interrupt ? If its an Interrupt, is it correct that the registers content is maintained? A9. After wake-up is occurred, resisters content is maintained. Q10. [PMU]The state diagram shows that the wakeup from Deep Sleep goes to Sleep mode and then IDLE. Is it possible to go from Sleep to Slow or Run? Can this be programmed? A10. You cannot program sleep mode. It is possible to go from deep sleep to slow or Run. Q11. [PMU]What software requirements are needed before entering Sleep or DeepSleep mode? A11. You cannot enter to sleep mode. You can think that there is no sleep mode in power management. [SPI] Q12. [SPI]What is the max speed of SPI ? A12. Max frequency of SPI is 1/4 FCLK. (it is 1/2 of BCLK and BCLK is 1/2 of FCLK) For example, if the CPU Speed is 80Mhz, the max speed of SPI will be 20Mhz. [GPIO] Q13. [GPIO]We want to use a 4 x 4 keyboard matrix and use the other pins as MultiFunction pins (UART). Is it possible? A13. You add to fullup resist (4.7k) on the pin(TXD) of IrDA(TFDU6102) Our Keyboard state is opendrain.When using both function keyboard and others... must add to fullup resist Ex) use 5x5 Keyboard matrix and use UART 2, 3 *Amuxctl = 0x0; *Amuxsel &= ~0x1f1f;; *Amuxsel |= 0x6060;; [RTC] Q14. [RTC]Is there any specific external pin to power on the RTC internal circuitry while powering off the microcontroller itself, instead of powering on the whole IC in deep sleep mode. A14. The 7202 don't have this function. [SMI] Q15. [SMI]Is it necessary to have SRAM in the board in order to debug SW on it? Is not possible to allocate this info for debugging in the SDRAM if we leave enough place on the SDRAM? A15. The SRAM is needed when you develop sample board.When you mass-produce, it is not necessary. Most of customer uses this with debug board. [UART] Q16. [UART]The 7202 has pins for 4 UARTs + IrDA. But I think we cannot use 4 UARTs + IrDA. One UART is internally used for IrDA (if activated). Is this right ? A16. Yes, you are right. The UART 1 used as IrDA. Q17. [UART]What should be the baud rate and the com port settings for communicating with the 7202 reference board ? A17. Baud Rate: 57600, set as NULL MODEM [ETC] Q18. [ETC]Is it possible to put a crystal instead an oscillator for both frequencies: 32,768KHz and 3,6864MHz? A18. We are already using crystals (for 32.768KHz and 3.6864MHz), Refer to our 7202 Reference board schematic sheet2 for the details. Q19. [ETC]Which is the capacitance of the 3,6468MHz and 32,768KHz frequencies input pins? We need this data to select the appropriate crystal capacitances. A19. Refer to our 7202 Reference board schematic sheet2. Q20. [ETC]Is it necessary to put as many decoupling capacitors of ceramic and tantalum type as in the development board at the 7202 power lines? Which is the capacitance required? Have you test using less capacitance? Is the core voltage increase, going to lower the required de coupling capacitance? A20. Usually, one capacitance is used for each line in 7202. It is for the power stability and is customary. If you want to reduce the number of capacitance to cut costs, you should test the stability with reducing the number of capacitance. Q21. [ETC]Which options exist to load new code to the flash ? A21. 7202 reference board has two type of Flash memories. One is for 16bit mode , and the other is for 32bit mode. You can select it with JP203, JP105 and JP106. Refer to the 7202 reference board application note. (It is also written on the PCB.) Q22. [ETC]How much current does 7202 consume in a deep-sleep mode? A22. In deep sleep mode, - I/O + Analog : 20uA - Core + PLL : 20uA [F/W] Q23. [F/W]Does the 7202, after not having found a boot code on the zero static memory position, jump to any other position or try to download the boot from any UART, USB or any other way? A23. NO. 7202 reference board boots from Flash memory now. USB, UART.. any other way is not available. Q24. [F/W]How can you download the boot code to the parallel E2PROM or Flash? Through the JTAG? Through the USB? A24. To download the boot code at Flash, you can use JTAG, serial or USB. but you should use an EEPROM writer to download it at EEPROM. Q25. [F/W]The problem is that the program "crashes" when an interrupt occurs , e.g. IRQ, since the flash memory is currently not initialized (IRQ exception vector is at a low adress). Is there a setting to make the CPU to jump to SDRAM instead of flash when a IRQ occurs (or reset)? (We have a 2MB flash and 8MB SDRAM.) How do you solve this on your reference board when you run the program in SDRAM? A25. It depends on your software. I mean there is many ways to handle exception. So I think that it's ok as long as you have right exception code in Flash ROM which started at 0. [OS] Q26. [OS]How do I transfer files from a Linux Directory on the PC to a Linux Directory on the Development Kit ? A26. I'm use to SAMBA server, between Linux and windows for file transmission    /etc/samba/smb.conf     # Samba config file created using SWAT    # from amba (127.0.0.1)    # Date: 2001/11/09 01:30:12    # Global parameters    [global]    workgroup = HPC <- Your workgroup    server string = Samba Server    security = SHARE    passwd program = /usr/bin/passwd %u    passwd chat = *New*UNIX*password* %n\n    *ReType*new*UNIX*password* %n\n    *passwd:*all*authentication*tokens*updated*successfully*    unix password sync = Yes    log file = /var/log/samba/%m.log    max log size = 0    socket options = TCP_NODELAY SO_RCVBUF=8192 SO_SNDBUF=8192    dns proxy = No    printing = lprng    [HLDK]    comment = MagnaChip 720X Linux Kit    path = /home/HLDK    public = Yes    writable = yes    # read only = No    hostname decision (amba)    reference files    /etc/HOSTNAME    /etc/sysconfig/network    ex) /etc/HOSTNAME    amba <-    ex)/etc/sysconfig/network    NETWORKING=yes    HOSTNAME=amba <-    GATEWAY=    GATEWayDEV=    command :    /etc/rc.d/init.d/smb restart    Shutting down SMB services : OK ]    Shutting down NMB services : OK ]    Starting SMB services : OK ]    Starting NMB services : OK ]    chmod 777 /home/HLDK/tmp <- read write mode [USB] Q27. [USB]Is it possible to use the 7202 internal USB transceiver, connecting directly the USB connector to the USB pins of the 7202? A27. Yes. 7202 reference board is using internal USB transceiver now. (Also, we made the board for using an external transceiver at option.) Q28. [USB]The introduction in the data sheet talks about the USBD's internal ROM. However, it does not say what's contained in this ROM. A28. In that ROM, there are descriptors. Below is all descriptor Table in the ROM. The first Hex number in each line is the offset from device descriptor index base address. And the second one is the value which ROM has in that location. The last one is comment for each value.    =========== DESCRIPTOR ============    DEVICE OFFSET DATA DESCRIPTION    0x00 0x12 length    0x01 0x01 DEVICE    0x02 0x00 spec version 1.00    0x03 0x01 spec    0x04 0xff device class         *******    0x05 0xff device sub-class         *******    0x06 0xff vendor specific protocol *******    0x07 0x08 max packet size    0x08 0xb4 vendor id         *******    0x09 0x05 vendor id         *******    0x0a 0x18 product id         *******    0x0b 0x00 product id         *******    0x0c 0x01 device release #    0x0d 0x00 device release #    0x0e 0x00 manufacturer index string    0x0f 0x00 product index string    0x10 0x00 serial number index string    0x11 0x01 number of configurations    CONFIG OFFSET DATA DESCRIPTION    0x0 0x09 length of this descriptor    0x1 0x02 CONFIGURATION (2)    0x2 0x20 total length includes endpoint descriptors (should be 1 more than    last address)    0x3 0x00 total length high Byte    0x4 0x01 number of interfaces    0x5 0x01 configuration value for this one    0x6 0x00 configuration string is here, 0 means no string    0x7 0x80 attributes - bus powered, no wakeup    0x8 0x32 max power - 100 ma is 50 (32 hex)    // now provide interface descriptor(s)    // first interface descriptor for alternate setting 00    0x9 0x09 length of the interface descriptor    0xa 0x04 INTERFACE (4)    0xb 0x00 Zero based index 0f this interface    0xc 0x00 Alternate setting value (?)    0xd 0x02 Number of endpoints (not counting 0)    0xe 0xff Interface class, ff is vendor specific         *******    0xf 0xff Interface sub-class         *******    0x10 0xff Interface protocol         *******    0x11 0x00 Index to string descriptor for this interface    // now provide endpoint 1 descriptor    0x12 0x07 length of this endpoint descriptor    0x13 0x05 ENDPOINT (5)    0x14 0x01 endpoint direction (00 is out) and address    0x15 0x02 transfer type - 00b = control, 01b = iso, 10b = bulk, 11b = int    0x16 0x20 max packet size - low 16 Byte    0x17 0x00 max packet size - high    0x18 0x00 polling interval in milliseconds (1 for iso)    // now provide endpoint 2 descriptor    0x19 0x07 length of this endpoint descriptor    0x1a 0x05 ENDPOINT (5)    0x1b 0x82 endpoint direction (80 is in) and address    0x1c 0x02 transfer type - 00b = control, 01b = iso, 10b = bulk, 11b = int    0x1d 0x20 max packet size - low (16)    0x1e 0x00 max packet size - high    0x1f 0x00 polling interval in milliseconds (1 for iso)    STRING OFFSET DATA DESCRIPTION    0x0 0x02 size in Bytes (including leading 2 Bytes)    0x1 0x03 STRING type (3) Q29. [USB]The data sheet says that the CPU can access the internal ROM. It doesn't say how this is accomplished. A29. There are 3 descriptor value-groups which can be modified by CPU. I put 7 *'s (*******) to them in the end of the line. Please refer to above table. And they, the groups, can be accessed like a register, READ and WRITE. You can see the register address and short description for each group in our SPEC. Like this, Address: 0x80012018, Name: DEVID, Default Value when initialized: 0x720205b4 Address: 0x8001201C, Name: DEVCLASS, Default Value when initialized: 0xFFFFFF Address: 0x80012020, Name: INTCLASS, Default Value when initialized: 0xFFFFFF Q30. [USB]As I interpret the data sheet the USBD handles SETUP tokens and EP0 communication internally. If this is the case, why is there a software interface to EP0? How can software use the EP0 interface? A30. In my opinion, if one needs to send or receive vendor specific commands through Endpoint 0, this interface to EP0 will be used. Q31. [USB]What is the purpose of the DEVID register? A31. If one makes a USB device with this 7202 chip, there must be a need to change NAME of that. Instead of 0x720205B4, one can put another name in that register (when enumeration, descriptor value). Q32. [USB]USB class codes are comprised of class, subclass and protocol, total in 24 bits. The DEVCLASS and INTCLASS registers, however, are 32 bits wide. Which bits correspond with the above fields? A32. Because our CPU internal bus width is 32bit wide, we paddled 8 0's to [31:24] field. And in the above descriptor table, the value in lower address offset corresponds to the more LSB side.One example, CLASS is to [7:0], SUB-CLASS is to [15:8] and PROTOCOL is to [23:16]. Of course, [31:24] field is always 8 0's. Q33. [USB]Does the USBD support string descriptors? A33. 7202 USBD doesn't support string descriptor. Q34. [USB]What is missing compared to a USB 1.1 Device Controller?" A34. [USB]As far as we know, there are some differences in 'Electrical spec.' between USB 1.0 and USB 1.1. The answer is fit to the case of 7202, but there are some supplementary explanations for customers to comprehend. The purposes of changing 1.0 into 1.1 are as following. Fix problems Remove ambiguities No changes to devices No changes to host controllers 1.0 SW must work on 1.1 HW Interoperability between all 1.0 and 1.1 stuff We think that there is no missing. The exact differences between USB1.0 and 1.1 except the electrical specifications are shown in this site: http://secure.nexusds.com/usb/discussions/_USB-Posted-articles/00000035.htm [FAQ 1] When TX FIFO data is transferred in 7202 USB block (PC-IN packet), Data out order (32Bytes size) is MSB Byte first and LSB Byte last. But To become correct operation, order is LSB first and MSB last TX FIFO 4Bytes MSB                                                   LSB 1 2 3 4 Data out order [1 - 2 - 3 - 4] But 7202 USB TX sends Data out order [4 - 3 - 2 - 1] in 1 Word [4 Bytes] So we swap the 4 Bytes Data order in application program. unsigned int swapByte(unsigned int dwdata) { unsigned int temp; unsigned int swapdata = 0; temp = dwdata; swapdata |= (temp >> 24) & 0x000000ff; temp = dwdata; swapdata |= ((temp >> 16) & 0x000000ff) << 8; temp = dwdata; swapdata |= ((temp >> 8) & 0x000000ff) << 16; temp = dwdata; swapdata |= (temp & 0x000000ff) << 24; return swapdata; } [FAQ 2] 7202 USB Data sheet has some bugs. One of bugs is not to support some setup request.But it can be solved by software. You should insert codes into USB software. If below code is inserted,heartbeat is not needed in 7202 USB program. typedef struct { union { unsigned int data[2]; struct { unsigned char bmRequestType; unsigned char bRequest; unsigned short wValue; unsigned short wIndex; unsigned short wLength; } pkt; } u; } USL_SetupData_t; USL_SetupData_t     cmd; In initialization coding part: You should set USBendpctrlEP0En(bit 0) in USBendpctrl's register (0x80012004). _outw(USBendpctrl, USBendpctrlEP1En | USBendpctrlEP2En | USBendpctrlEP0En); _outw(USBintmask,_inw(USBintmask)&~ (USBintmaskMKusbreset|USBintmaskMKsetup)); In USB interrupt service routine if((status & USBstatususbreset) && !(mask & USBintmaskMKusbreset)) { } else if((status & USBstatussetup) && !(mask & USBintmaskMKsetup)) { cmd.u.data[0] = _inw(USBsetup0); cmd.u.data[1] = _inw(USBsetup1); if (cmd.u.pkt.bRequest == 0x01){ //check ClearFeatureSetup Request val = _inw(USBendpctrl); if (cmd.u.pkt.wIndex & 0x01) { val1 = USBendpctrlEP0Rst | USBendpctrlEP1Rst; } else if ( cmd.u.pkt.wIndex & 0x02) { val1 = USBendpctrlEP0Rst | USBendpctrlEP2Rst; } _outw(USBendpctrl,val1); for (i=0;i<10;i++); _outw(USBendpctrl,val); } }