Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1.Can I directly connect the 32.768 KHz and 3.686 MHz signals to the Processor.If yes ... what is the typical duty cycle etc that the processor may require ? A1.Yes, direct clock input from other logic is OK, but MagnaChip recommend to use 50% ± 5% duty cycle clock. Because there are some logics have to work with half phase delayed clock(1/4 timing delayed clock) and the original clock.3.6864 Mhz source clock is re-fined duty and multiplied frequency at internal block of PLLs, so some duty variation maybe OK but we can not sure. If possible, try to use 50% ± 5% duty clocks. Q2.The Microbuddy boots up with a default value of 2 MHz instead of 3.686MHz ? Can the MagnaChip processor operate correcly at this frequency. What I intend doing is running code out of the FLASH and writing to the Microbuddy to initialise it to run at 3.686 MHz. Will there be any issues of processor stalling etc due to sudden jump of frequency from 2 MHz to 3.686 MHz. A2.PMU and PLLs of HMS30C7201 made for 3.6864MHz input clock and MagnaChip do not garentee with other input clock. But there may be some marginal range for input clock.If 7202 worked fine with somewhat higher or lower clock by customer's experiments, then user should have to check the voltage of PLLFILT pins. In normal, PLLFILT pin stay about 30%~70% of PLL VDD. If PLLFILT voltage goes too close to PLL VDD or ground("0"), PLL will not work fine.If user wanted to use two input clock in field, input clock shoud be changed during deep sleep state. Q3.As I understand from the MagnaChip Data sheet: 1. The processor can be put to Deep sleep Mode by writing either 0x07 or 0x0F to the PMU Mode register. 2. The processor can be brought out of the Deep sleep mode when either, some or all of the following signals are asserted: (a) nPMWAKEUP is brought low (The PMUresetStatus reads D4= 1 when this happens) (b) Port A interrupt (The PMUresetStatus reads D4= 1 when this happnes) (c) MRING is brought low (The PMUresetStatus reads D5= 1 when this happens) (d) RTC wake up (The PMUresetStatus reads D6= 1 when this happens) Question) How do we differentiate between event (a) and event (b)? i.e. Port A interrupt event waking from Deep Sleep Mode and the nPMWAKEUP signals event waking from deep sleep. A3.The differnce of above two signal is "signal type". It means, there's no way to stop external signal from "nPMWAKEUP" pin, but Port A signal can be masked with S/W. Basically all external signal can not be masked for wakeup.In 7201, user only can mask pmu interrupt events (mask interrupt signal from PMU to interrupt controller) but always 7201 wake up from deep sleep when any event of above four wakeup signals occurs. Q4.If we wish to say just wake the processor up by MRING signal .. is there any way to do it ? The mask bits D9 (OnEvt Interrupt enable), D10(MRING Interrupt Request/Clear), D11 (RTC Wakeup interrupt Request/Clear) don't seem to have an effect. I tried the following: (a) Set the PMUResetStatus=0x1ff( to reset all pending status bits ) (b) Disable Rtc interrupt by writing 0x00 to RTCCR (c) Set the PMUResetStatus=0x400( to allow mring to waker the processor up) (d) Save the PMUMode (e) write 0x07 to PMUMode (f) LOOP for 1ffff times (The PMU enters deep sleep mode) Now if I assert any of the wakeup signals i.e. MRING or nPMWAKE UP .. the processor wakes up. If my understanding is correct ... since I set only D9=1 in the PMUResetStatus i.e. step (c), the nPMWAKEUP should not have any effect. A4.As mentioned in A3, external wakeup signals can not be masked for wakeup.you can see this when you check "ResetStatus register value", mask bit just related with interrupt event to inform interrupt controller. Q5.The steps given to enable the wakeup of processor by nPMWAKEUP signal on page 7-7 of the databook (Enable the nPM WAKEUP interrupt but by writing 0 to bit 9 of the ResetStatusResgister) is different from what is suggested in table 7-6 i.e Bit =1 Enable PMU interrupt from nPMWAKEUP. Can you please let me know which of the two statements are correct ? A5.We made mistake in page 7-7, sorry for your confusing about this.Table 7-6 is correct. Q6.Does the processor go into idle (on the way to deep sleep) as soon as the PMU_MODE register is written to, or can the processor run for a few more cycles (and instructions) before the PMU stops its clock? What is the purpose to wait after idle, surley all the clocks will be running, the SDRAM controller will be running etc as soon as the processors clock starts running and executing code again? A6.When PMU_MODE register set to go deep-sleep, PMU try to get bus mastership, so after that CPU should not work normal instruction. If PMU got bus mastership, Chip could go to deep sleep mode.If still there's DMA operation, PMU should had to wait to get mastership. (usually, programmers make all functions disable before go to deep sleep but an external event might disturb deep-sleep operation) Q7.I notice in the MagnaChip test code file pmutest.c you flush the write buffer(SDRAMC) just before going into deep sleep, and also have a delay before and after deep sleep (fragment of code below). What is the reason for this and is it required? A7.For SDRAM flush matters, We recommend flushing SDRAM write buffer, before goint to deep-sleep, to be sure data from unstable clocks operation of wake-up event.(to get rid of the chance of SDRAM write(back) buffer data corruption) Sometimes it is unpredictable the very first half clock duration is Ok or not, when PLL starts first or starts again. (In real, Mask signal could make short duration by some delay) So after exit from deep-sleep, we wait some cycles for clock stable. Q8.Some SDRAM's require a bust of refresh cycles after exiting self refresh because the refresh counter inside the SDRAM is different for normal refresh and self refresh. Is there any need for a bust of refresh cycles after exiting deep sleep with the HY57V641620HG or can the refresh controller inside the GMS30C7201 just be left to refresh 4096 cycles every 64ms? A8.It is enough just refresh 4096 cycles every 64ms after deep sleep mode. Q9.When the GMS30C7201 is powered on .. the PLL3 freq. is at 49.7664 MHz.We write to the Clkctl register to increase this to 59.xxx MHz.For doing this we set bit[6] = 1 and write the appropriate data to the CLKctl register (see page 7-4 of the databook). Will this gurantee at all times that PLL freq. is changed instaneously or we have to follow the alternate method that MagnaChip has recommended i.e. writing to the Clkcntrl register with bit[6]=0 .. taking the processor to deep sleep mode and then waking it up using an interrupt ? Is there a delay required after we write to Clkcntrl register with bit[6]=1. A9.If PLL frequency changed, PLL output signal could be unstable during PLL lock time. In default state, PMU designed that PLL frequency will be changed at wake up time from deep sleep mode. But, if Bit[6] of Clkctl register is set, frequency setting value transfer to PLL at once and PLL will change output clock frequency.In Clkctl register there's another option of MUTE, it used to prevent propagation of unstable clock by ANDing with PLL lock signal. So even though user set bit[6] to change clock at once, MUTE function may cause delay of new frequency clock output.MagnaChip recommends PLL frequency changing via deep sleep states and some dummy wait loop before and after clock frequency setting operation to be stable.