/**
 *******************************************************************************
 * @file        hal_scu_version.txt
 * @author      ABOV R&D Division
 * @brief       specific version for SCU
 *
 * Copyright 2022 ABOV Semiconductor Co.,Ltd. All rights reserved.
 *
 * This file is licensed under terms that are found in the LICENSE file
 * located at Document directory.
 * If this file is delivered or shared without applicable license terms,
 * the terms of the BSD-3-Clause license shall be applied.
 * Reference: https://opensource.org/licenses/BSD-3-Clause
 ******************************************************************************/

/**
 * @addtogroup  HAL HAL (Hardware Abstraction Layer)
 * @{
 * @defgroup    HAL_SCU SCU
 * @{
 * - System Control Unit (SCU) controls or configures system as for the three major functions below.
    -# Clock
    -# Reset
    -# Operating mode
 * - Reset and clock should be controlled carefully to maintain optimized system performance and power dissipation.
 * - Core, Clock, Low Voltage Detector and Power blocks are sub-systems of SCU.
 *
 * <B> [ SCU version per ABOV 32bit chipset] </B>
 *
 * <table>
 * <tr> <td> <center><B> ABOV ARM Cortex-M 32bit </B></center>
 * <table>
 * <tr>
 *     <td> <center><B>A31xxxx series\n Cortex-M0+</B></center>\n
 * <table>
 * <tr>
 *     <th > <center>Type</center> 
 *     <th> <center>Version</center> 
 *     <th> <center>Chipset</center>
 * <tr><td> <center>F</center> <td> 01.00.00 <td> A31G11x, A31G12x
 * <tr><td> <center>V</center> <td> 01.00.00 <td> A31G31x
 * <tr><td> <center>V</center> <td> 01.00.01 <td> A31G21x
 * <tr><td> <center>V</center> <td> 01.00.02 <td> A31G22x
 * <tr><td> <center>V</center> <td> 01.00.03 <td> A31G32x
 * <tr><td> <center>V</center> <td> 01.00.04 <td> A31T21x
 * <tr><td> <center>F</center> <td> 01.01.00 <td> A31L21x, A31L12x, A31L22x
 * <tr><td> <center>V</center> <td> 04.00.00 <td> A31C14x, A31C12x
 * <tr><td> <center>F</center> <td> 02.00.00 <td> A31G33x, A31G34x
 * <tr><td> <center>F</center> <td> 01.00.01 <td> A31S13x
 * </table>
 *     <td> <center><B>A33xxxx series\n Cortex-M3</B></center>\n
 * <table>
 * <tr>
 *     <th > <center>Type</center> 
 *     <th> <center>Version</center> 
 *     <th> <center>Chipset</center>
 * <tr><td> <center>V</center> <td> 03.00.00 <td> A33G52x, A33G53x
 * <tr><td> <center>V</center> <td> 02.00.01 <td> A33M11x
 * <tr><td> <center>N/A</center> <td><center>N/A</center><td><center>N/A</center>
 * <tr><td> <center>N/A</center> <td><center>N/A</center><td><center>N/A</center>
 * </table>
 *     <td> <center><B>A34xxxx series\n Cortex-M4</B></center>\n
 * <table>
 * <tr>
 *     <th > <center>Type</center> 
 *     <th> <center>Version</center> 
 *     <th> <center>Chipset</center>
 * <tr><td> <center>V</center> <td> 02.00.00 <td> A34M41x
 * <tr><td> <center>V</center> <td> 02.00.04 <td> A34M42x
 * <tr><td> <center>V</center> <td> 02.00.05 <td> A34L71x
 * <tr><td> <center>N/A</center> <td><center>N/A</center><td><center>N/A</center>
 * <tr><td> <center>N/A</center> <td><center>N/A</center><td><center>N/A</center>
 * <tr><td> <center>N/A</center> <td><center>N/A</center><td><center>N/A</center>
 * </table>
 * </table>
 * </table>
 * @}
 *
 * @defgroup    HAL_SCU_CLK SCU_CLK
 * @{
 * - A SCU Clock is one of the System Control Unit(SCU) subsystem.
 * - This system provides high/low speed clock oscillated by internal oscillator and external oscillator.
 * - There is a Phase-Locked Loop (PLL) block that oscillates based on the high speed internal/external 
 *   clock for more faster system and peripheral operating.
 * @}
 *
 * @defgroup    HAL_SCU_LVD SCU_LVD
 * @{
 * - A SCU Low Voltage Detector (LVD) is one of the System Control Unit(SCU) subsystem.
 * - This system provides to detect unstable power supply and notifies the danger or 
 *   generates system reset itself.
 * @}
 *
 * @defgroup    HAL_SCU_PWR SCU_PWR
 * @{
 * - A SCU Power is one of the System Control Unit(SCU) subsystem.
 * - This system consists of some operating mode such as INIT mode, RUN mode, SLEEP mode, 
 *   DEEP-SLEEP mode, DEEP-SLEEP2 Mode.
 *   -# INIT mode 
 *     * An Initial state of the chip when a reset is asserted.
 *   -# RUN mode 
 *     * The maximum performance with high-speed clock system.
 *   -# SLEEP mode 
 *     * Used as a low power consumption mode by halting processor core.
 *   -# DEEP-SLEEP and DEEP-SLEEP2 mode 
 *     * Used as a low power consumption mode by halting processor core and unused peripherals.
 * @}
 */

/** @} */

